What is This Testbenches required for verifying circuit performance List what testbenches are used for each of the electrical parameters to be tested, and briefly describe the testbench circuit setup and how it measures the specified parameter. Stuff, Anyhow? Do you mean • test schematics in the EDA toolchain? • virtualized (i.e., access restricted through the caravel digital infrastructure) test circuits on silicon? • stand-alone test circuits with dedicated I/O pads on silicon that bypass the digital on-chip virtualization layers? • off-chip test benches?

There was another question involving off-chip testing. This question is just about simulation. What testbenches are needed to characterize the circuit. This does not need to be very detailed or specific. Just something like "gain-bandwidth: Measured with AC analysis from 100Hz to 1GHz. Testbench setup uses a dependent voltage supply to force INN = 0.5 * OUT; AC is applied to INP".

OK, here you go: A virtual potbox along the lines of this contraption, with a grossly simplified (I still need to get through design tool installation and version hell, git pull --all totally breaks my sort-of-kind-of working Telluride 2021 setup, and get some idea how to avoid the RISC V installation and configuration hell altogether) version of this weirdness thrown in, designed bottom-up from matching layout primitives, avoiding as many "APIs" between different building blocks assigned to different designers that specify anything other than layout-level matching structures as possible. Wherever absolute quantities are specified by a software engineering suit who thinks this sort of thing is a good idea, implement specifications like Output Voltage (vbgsc) 1.024V For precision DAC reference Output Voltage (vbgtc) 1.048V For thermocouple reference with no regard for avoiding area-hogging precision passive components and digital trim bits required whatsoever. Limiting factor will be the consistency of the xschemrc etc. scripts between Telluride 2021 and the present, and the explicit (for an analog design, not a software engineer) documentation of all the changes. That's the version to make Mr Potbox's life easy. What do the review committees need to prevent them from eliminating me from their challenge?

"_What do the review committees need to prevent them from eliminating me from their challenge?_"---A proposal, more or less formal, that follows the rules identified up at the top of this channel:

Proposal must be in PDF format unless otherwise approved (assuming that most formats will export PDF).
	Provide (short) CVs of designers, separately from the proposal
	Specify the IP block to be designed
	Specify the architecture to be used and how the specification will be achieved
	Indicate any likely challenges (e.g., difficult-to-meet specification)
	Specify any resources needed (e.g., external current source)
	Any additional circuitry or test points required for measurement of the block as a standalone IP must be noted.
	External resources must be open source.
	Circuits from external sources may only be used outside of the IP (such as a testbench) unless it is part of Chipalooza (e.g., the current bias generator).
	If more than one IP block is proposed by the same group, rank by preference in case of duplicate proposals.
	Any departure from specified pinout must be noted (and approved).
	The proposal must contain a plan for how the IP block will be connected into a Caravel user project environment, and how it will be tested and measured for characterization.
	The proposal may be submitted by posting to this channel or emailing to <mailto:shuttle@efabless.com|shuttle@efabless.com>