@Tim Edwards Sorry, I am a little confused on the 1.8V LDO design. As said, it’s used for powering BG1.8V. if so, what is the reference voltage for the LDO. and what is the pin difference between digital power 1.8V and out voltage 1.8V in the pinout of LDO block? Thanks!

The digital power supply

dvdd

is only meant to be the reference for the

ena

input. It might not be needed as a pin for the IP block. However, there is still an expectation for the Caravel implementation that the

vccd

domain (1.8V) is provided from an off-chip source. So there will be a digital domain that determines the level of the enable input. The reason for having the LDO driving a separate 1.8V domain is to make sure it is regulated and not subject to the noise, variation, and other unknowns of the off-chip supply.

@Tim Edwards thanks. so I take it as the voltage power domain for the ena signal. I am wondering why not use avdd as the voltage power domain for ena signal. and sorry I am still confused. what is the reference for the LDO to generate 1.8V? Will we use the BG output as reference to generate the 1.8V? It's confusing that 1.8V LDO is to power BG, then before that, how BG works? I am not sure if I have describe my idea clearly.

The idea is that there are two separate 1.8V supplies, an external one (potentially very noisy) that drives all the on-chip digital, and one which is internal (coming from this LDO). You might very well want to make the enable signal come from 3.3V so even if it comes from the digital domain, it has to be run through a level shifter that will help isolate it from the noise in the digital system.