I'm simulating the behavior of a static CMOS inverter in SKY130 process with Ngspice.
This is my circuit:
Inverter example
v1 net1 GND pwl 0 1.8
v2 net2 GND pwl 0ps 0 100ps 0 150ps 1.8 500ps 1.8 550ps 0 1ns 0
x1 net2 net3 net1 GND inverter
*CLoad net3 GND 10fF
.lib /opt/open_pdks/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
.tran 20p 2n
.save all
*.print v(net3)
.plot v(net3) v(net2)
.subckt inverter in out vdd vss
XM2 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.65 nf=1 ad='W * 0.30' as='W * 0.30' pd='W + 2 * 0.30'
+ ps='W + 2 * 0.30' nrd=0 nrs=0 sa=0 sb=0 sd=0 mult=1 m=1
XM1 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.30 nf=1 ad='W * 0.30' as='W * 0.30' pd='W + 2 * 0.30'
+ ps='W + 2 * 0.30' nrd=0 nrs=0 sa=0 sb=0 sd=0 mult=1 m=1
.ends
.GLOBAL GND
.end
I tried with an external load of 10fF and with no load. (figure 1 and figure 3)
The first case works as expected.
In the second case I noted a strange behavior on the falling output at time 150ps (figure 2 with zoom of the output).
There is an oscillation instead of a exponential decrease as should be.
I searched in VLSI books for example CMOS VLSI Design: A Circuits and Systems Perspective, but I didn't find any explanation of this behavior.
My question: it is only a problem of numerical convergence because there is no load on the output (only parasitic capacitances that appeaer low )or this really happens?
If it happens, why?