Has anyone written firmware for spi ? Or an example? @Matt Venn @Tim Edwards @Mitch Bailey I want to transmit data from chip to slave spi. I found demo codes for serial on repo but no spi

@samarth jain: See in the

caravel_mgmt_soc_litex

repository the testbench

verilog/dv/tests-standalone/spi_master

.

Why for spi we need gpio 1 is input. It’s actually Sdo output !? And what config we should do for other gpio 2,3,4 ? @Matt Venn @Tim Edwards

@samarth jain: I thought you wanted to use the SPI master. GPIO 1 to 4 is for the SPI slave (housekeeping). The SPI master is on GPIO 32 through 35 (32 = sck, 33 = csb, 34 = sdi, 35 = sdo).

😅 it was not clear in documents, yes I needed spi master. Is my code correct? I have doubts regarding the gpio configs as mentioned in previous post @Tim Edwards

@samarth jain: I'm not as familiar with the SPI master on the VexRISC, but there is a clock divider register that determines the SCK rate (there's also a "control" register but I don't know what the bit fields are without looking it up in the docs).

#define reg_spimaster_clk_divider   (*(volatile uint32_t*) CSR_SPI_MASTER_CLK_DIVIDER_ADDR)

Yes I have tried it

But you have set the clock divider to the highest value, which would be the slowest possible clock.

Making divider to zero makes frequency slower. Clock divider increases frequency. @Matt Venn @Tim Edwards

Okay. As I said, I'm not familiar with the implementation.

Sure Tim, who would be able to help me answer the spi clk max speed @Tim Edwards .As per my testing I used DLL and got only 200KHz , hence I plan to try higher multiplier for system clk. I need faster spi

@samarth jain : The SPI master is defined here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/spi/spi_master.py and instantiated in

caravel_mgmt_soc_litex

in

litex/caravel.py

as:

# Add a master SPI controller w/ a clock divider
        spi_master = SPIMaster(
            pads=platform.request("spi"),
            data_width=8,
            sys_clk_freq=sys_clk_freq,
            spi_clk_freq=1e5,
        )
        spi_master.add_clk_divider()

I could not determine with a quick look how the clock divider works. The

spi_clk_freq

is set to 1e5 "in Hz" although I have no idea how they determine what a "Hz" is in a system whose rate depends entirely on an external clock source (this is just one of the many stupidities of the whole LiteX system). But if somewhere the global rate of 10MHz is used for LiteX and that's consistent throughout the code, then the SPI has been configured to run at the slow, slow maximum rate of 100kHz, but I'm guessing that the value put into LiteX for the core clock rate was 40MHz (the maximum clock rate), so that if LiteX computed a 100kHz SPI master at 40MHz core clock, then it comes to 25kHz with the 10MHz clock on the development board. (All of this worked so much better when we (I) used the PicoRV32. The CPU was hopelessly crippled by switching to the LiteX VexRISC. I tried hard to prevent that switch but I got overruled). The best you can do is to get the CPU rate up from 10MHz on the board to 60 or 70MHz off of the DLL; if you additionally increase the

vccd

supply to about 2V, you can potentially get the core clock rate up to 100MHz, but I don't think you will ever get the SPI master much above 200kHz. You can try Marwan Abbas for additional questions (he has been writing the test code for characterizing blocks like the SPI master), although I think the analysis above is about as thorough as you're going to get.

Hi @Marwan Abbas is it possible to change the spi clock in next run of mine? Can tell me how I can go about it? @Tim Edwards. Like can I route it to cpu clk to spi divider logic?

Yes, I think there is a divider for the SPI, but I couldn't find the register information right away.

The spi Clk itself is limited to 100khz , the divider will reduce clk further? I wanted to increase this limit to cpu Clk if possible in my next tapeout. Will that be possible?