60 GHz VCO, still ongoing 🙂 • Done (more or less): ◦ CCP ◦ Varactor banks ◦ Inductor plus guard ring ◦ Buffer fet connections • To do: ◦ Buffer loads (microstrips) ◦ CCP current mirror ◦ RF pads ◦ Biasing, biasing everywhere! ◦ Figure out about the placement of density tiling inside the top cell (HALP!) Simulations tells me that it oscillates at around 60GHz with a FTR of 4.5% (taking into account most of the parasitic loading sans inductances) Thread in Slack Conversation