Hi all, I've been playing with magic and klayout for a while now and I see differences in the DRC results with the files provided. Klayout seems to be much more permissive than the rules supplied for magic. To further confuse things I've also found https://github.com/laurentc2/SKY130_for_KLayout which looks like it has a more complete set of rules than those provided for either magic or klayout. So, which set of rules should I use to stand the best chance of getting a layout that will actually work?

I think magic is given more TLC for sky130 than klayout. @Tim Edwards updated it a lot recently and is actually employed by efabless haha https://open-source-silicon.slack.com/archives/C016HUV935L/p1708137848574649?thread_ts=1708014341.160749&cid=C016HUV935L

@Roel Jordans: Due to significant lack of bandwidth, we have only ever developed the SkyWater "manufacturing rules" deck for klayout. This is a sign-off DRC deck that ensures that layouts we send to SkyWater don't get rejected. However, SkyWater only rejects rule violations that would cause issues with the mask-making process, which is mainly mask layer shape width, spacing, and area; and rule violations that cause issues with manufacture, which also includes the density rules. All other rules are considered by SkyWater to be at the user's own risk. If you were to submit a design directly to SkyWater, they would run a full DRC deck and require you to correct any manufacturing rule violations and to correct or waive any other rule violations. By contrast, the magic DRC rule deck contains a lot of the rules outside the manufacturing rule deck. However, magic is lacking some capability to detect certain rule types, especially those that are related to connectivity (such as "same net well spacing" vs. "different net well spacing"); so magic's rule deck isn't giving 100% coverage, but the rules it misses are generally going to be non-fatal (would be a problem for a production run, but not likely an issue for a test chip). Obviously, developing a full DRC deck for klayout would be the best option. If somebody wants to pay for that development. . .

Thanks @Tim Edwards for the elaborate answer! You mention that the rule misses for magic could be a problem for a production run. What kind of problems would you expect there? Are these mainly yield related or are there other things that may pop up?

@Roel Jordans: Since it's easy to implement basic width and spacing rules in magic, then it's the more obscure rules that sometimes I can't find a way to implement. There are a host of connectivity rules involving high voltage vs. low voltage nets that, if violated, could significantly shorten the lifetime of the chip, but probably not enough to be concerned about for a test chip. Violating different-net well rules can cause leakage, but unlikely to show up as more than an elevated current draw. Most of the obscure rules are just there to ensure good yield, which is the least worry for a test chip, since you only get back and test 10 parts, say, then you'll probably never notice a 5% yield hit.