Hello I am trying to run the caravel_user_project_analog following this link https://github.com/efabless/caravel_user_project_analog/blob/main/docs/source/index.rst. Whenever I am trying to run make verify-mprj_por, it gets 2 errors in caravel_netlists.v and example_por.v about some library not found.Here I defined paths like this --.export CARAVEL_LITE=0 export PDK_ROOT=$(pwd)/pdks export CARAVEL_ROOT=$(pwd)/caravel export SIM=RTL Please help me out.

You appear to be missing the HVL library

sky130_fd_sc_hvl

in your PDK, or else a path to it is not being defined somewhere.

HVL library is available. Could that be an issue with path definition?Thats how I defined paths export CARAVEL_LITE=0 export PDK_ROOT=$(pwd)/pdks export CARAVEL_ROOT=$(pwd)/caravel Any idea how I should modify the path definition?

Try removing

-DEF_STYLE

from the

iverilog

command options.

I am sorry,but I am a noob.Could you plz tell me how I can remove it?

What does

ls $(PDK_ROOT)/sky130A/libs.ref/*/verilog

return?

Sorry for late reply.It returns couple of file names.BTW,ls $(PDK_ROOT)/sky130A/libs.ref/*/verilog returns no such file error.But worked without parenthesis

In

verilog/dv/mprj_por/Makefile

there’s a line that sets

-DEF_STYLE

.

ifeq (,$(wildcard $(PDK_ROOT)/$(PDK)/libs.ref/*/verilog))
SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
endif

I think you can safely comment that out. But before you do that, are both

PDK_ROOT

and

PDK

defined in your environment?

Thank you for your reply.I commented out the line and defined PDK_ROOT and PDK. Still have the same issue.

@Md Omar Faruque You only need to use

caravel_user_project_analog

if you’re going to be using non-standard supply/ground voltages or relatively high performance signals that would be affected by the capacitance of devices in the standard gpio. I thinks there are 28 gpio cells that you can use for analog io in caravel (there is only a small resistor between the signal and the pad). The signal voltage must be between 0V and VDDIO (3.3V), though. It’s probably wise to use each gpio as either analog or digital, but not both. Be care when routing analog signals with digital flows. You might want to manually change the path width of the analog signals after routing.

Yes,I did export PDK_ROOT=$(pwd)/PDK and export PDK=sky130A.This is the result of env |grep PDK

Maybe it’s running in docker and the environment variable is not being passed. In

caravel_user_project_analog/Makefile

can you change line 66 to this?

-e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} -e PDK=${PDK} \

Yes,it got rid of this error. But,now it can not find mgmt_core.v file.However,as you suggested ,I am planning to switch user_project_example(digital).I have 2 question in this regard.1.Lets say I want to get 2.5V output.How should I do voltage mapping?If I write in wrapper, assign analog_io[0]=2.5; Is it correct? 2.I am a bit confused .I saw that analog pin gives up to 5.5V output if I use VDD=5.5V.Is it not like this?

2) I believe VDDIO will be your maximum voltage (1.8V-5.5V depending on configuration). So whatever you set that at. 1. Verilog does not deal in voltages, your

analog_io[0]

will be the pin name and you can output a 2.5V signal with that from an analog block.

@Mitch Bailey: It is possible to set a signal like

analog_io

to type

real

and give it a floating-point number value. The value won't be interpreted as meaning anything to verilog, but the modules can be made to treat it consistently as indicating a voltage. More often, though, power supplies are just set like digital signals as 1 (on), 0 (off), or X (invalid).