Hi All, I am doing post layout simulation with dummy transistors present in the circuit. There are several warnings after using

extratct all

command on flattened cell. The warnings are highlighted in the dummy cells. I am unable to find the file containing the warnings. Can anyone please help me with the issue? The GDS is attached.

@naina singhal after extracting, try

feedback save ext.warn

to save the warnings and coordinates to

ext.warn

.

Thank you so much @Mitch Bailey.Can you please have a look at the generated file and tell me what does it mean? I don't get what "connecting remainder to node" is?

Normally, mosfets are 4 terminal devices, gate, source, drain, and bulk. However, it is possible to use mosfet as a capacitor with the source and drain connected. When magic extracts a mosfet structure with only three connections, it says “device missing 1 terminal” and shows what node the missing terminal is connected to. The

pale

at the end is the marker color, I think. These are normally perfectly acceptable, and you shouldn’t be concerned with them. Do you have any other error types?

I have placed dummy transistors in my layout. I have shorted all the terminals of PMOS to VDD and all the terminals on NMOS to ground. The post layout simulation is not working. The gmin stepping is failing and OP simulation is aborted. is my connection of transistors wrong?

In klayout, you can use Tools -> Trace net to highlight connectivity. I’m not sure about magic.