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I've just tried the new ngspice42 verilator cosim feature - very nice. Here's the example: <https://sourceforge.net/p/ngspice/ngspice/ci/master/tree/examples/xspice/verilator/adc.cir>

I was able to adapt it for a simple R2R DAC I'm working on

just showing bit3 of the verilog driver and the output

question for <@U01819B63HP>  - I'd like to export the r2r subckt to use with this simulation, but hitting the netlist button results in a netlist that isn't setup to be a subckt

I need to remove the ** in front of the subckt and the ends

Is there a way of exporting with it as a functioning subckt?

<@U0172QZ342D>:  Sorry, had trouble finding it because apparently Stefan moved it recently.
Go to menu item `Simulation`-&gt; `LVS` -&gt; `LVS netlist:  Top level is a .subckt` and select it.