samarth jain
02/16/2024, 6:06 AMTim Edwards
02/16/2024, 1:53 PMvddio
can be dropped to 1.8V and the chip is supposed to work; I have dropped it to around 2.3V and could get it to continue working. Below that and other circuits on the board start dropping out. I have not looked at the absolute maximum (or rather minimum) ratings of the various chips. It's possible that the LDO is the first to drop out, which would mean you might be able to bring the voltage down further if you supply both the vddio
and vccd
supplies externally instead of relying on the LDO (note that the rev 5A board has a chip U4 on it which is a POR with a 3V threshold and prevents anything from operating at less than 3V unless you remove the chip and bypass the reset button).
There are also options on the GPIO for changing the threshold voltage. You might be able to maintain 1.8V communication with the chip by setting the input buffer trip voltage appropriately (or possibly it works as-is), and set SDO to be an open-drain configuration that you can pull up to 1.8V with a resistor so that it doesn't try to drive 3.3V into your FPGA.samarth jain
02/24/2024, 2:10 PMsamarth jain
02/24/2024, 2:11 PMTim Edwards
02/24/2024, 3:39 PMsamarth jain
02/24/2024, 3:45 PMTim Edwards
02/24/2024, 3:55 PM