Dear all (again)... I am doing LVS on a very simple circuit (common source amplifier: one transistor, one resistor, four ports), following instructions in detail (xschem subcircuit netlist, magic extraction using "extract all", "ext2spice lvs", "ext2spice". I have a link to the setup.tcl for the pdk in the working directory (setup.tcl -> /usr/local/share/pdk/sky130A/libs.tech/netgen/setup.tcl) However, when I run netgen (netgen -batch lvs file1 etc), I get a lot of property errors for the resistor and transistors (the circuit itself matches", such as: Model sky130_fd_pr__res_xhigh_po_0p35 pin 1 == 2 No property w found for device sky130_fd_pr__res_xhigh_po_0p35 No property w found for device sky130_fd_pr__res_xhigh_po_0p35 No property value found for device sky130_fd_pr__res_xhigh_po_0p35 No property w found for device sky130_fd_pr__res_xhigh_po_0p35 No property mult found for device sky130_fd_pr__res_xhigh_po_0p35 and similarily for the transistor. Is not the purpuse of the setup.tcl to avoid such parameter errors (they are not given in the xschem netlist)?

@Ted Johansson these are more warnings than errors. In the setup file, the devices are grouped by type and the parameters are handled accordingly. Are you getting actual property errors in the lvs result file? If so, it might depend on how you instantiated the symbols or maybe even a problem with the pdk. If you can share your repo (and lvs command), I’ll take a look.

Sure, what do you mean with repo? I will gladly share the netlists from xschem and magic, as well as the netgen lvs command I used.

Sorry, I assumed there was an associated github repo. If there isn’t, then a tarball would be fine.

Hi again. I found and solved the LVS property error. Although there is a long list of missing properties in the terminal window, I guess setup.tcl is taking care of this. The important information is in the output file (comp.out by default). The property errors boiled down to different sizes in resistor sizes. This actually comes from difference in the PDK schematic cell value for sheet res compared to the PDK layout pcell (total resistance including contacts, as confirmed by Tim Edwards). To get the same resistor value in both schematics and layout, you have to chose different L (in my case 0.988 vs. 0.5 um for used resistor). As netgen checks the resistor dimensions, not values, you get a property warning. Editing the netlists and changing to same L removed the property warnings.