this is the circuit of flop

In sky130 add this component in xschem:

sky130_stdcells/dfrtp_1.sym

See the example '`sky130_tests/test_stdcells.sch`'

@Stefan Schippers @ALOK PRATAP SINGH how to add this component ? in which library i dont know

the design in the image is the classic master-slave DFF using a tri-state inverter type configuration, but connecting the sources of the outer P and the N turns it into a transmission-gate version which is a bit faster since both the N and P assist in sampling during clock active time. Also, the 3-input nand-based design (like the old 7474 TTL IC) flop also works well. It is simpler and has dedicated *set and *reset inputs also . I haven't benchmarked it against the transmission-gate design but I think it would be nearly as fast, and definitely less clock CV2F power consumption. If you dont need *set *reset then it can be reduced to mostly 2-input nand gates. If you dont have much loading, the output inverters can be removed. Its been tested in 0.18u TSMC and XFAB.

@Piyush Dwivedi the Xschem library was written above:

sky130_stdcells/dfrtp_1.sym

, first term is the directory, second term after '/' is the cell DFF name.