Dear all, I am with Uppsala U, developing a new MSc/PhD course Analog CMOS IC design using open-source software and PDK. I have a long experience with CMOS analog/RF using Cadence from the industry. It is interesting that IC design now starts to be possible to do with open source tools, and good tools for teaching first-time students about IC design flow and basic tools! I have a few questions that relates to the layout in magic, but I think they are more PDK-related so I post the questions in this channel. Maybe you can help me?! 1. The sky130 PDK has a drawing grid of 0.005 um but still locked to 0.01 um snap in the .magicrc for the PDK. Is there a reason for this? When generating the layout from the xschemSPICE netlist, the transistor cell (sky130_fd_pr__nfet_01v8) is off-grid (the snap grid), which is not a large problem but does not look nice sometime when creating metal connects to the cell. Because of the snap, it is not possible to move the cell just one grid point. 2. In a design library (with the correct links to the PDK for xschem and magic), the results from repeatedly importing a SPICE netlist seem to be cached somewhere in the system. E.g. if I move my ports (e.g. devices/iopin.sym in xschem), do not save the layout, start with another empty magic window, and import the netlist again in the same design folder, there will be double ports in the layout if I moved ports around the in the layout: ”Port index 0 is already used by port inp. Use command "port index 0" to force equivalence after defining the port” I solved this by starting with a new fresh library (new name) if I need to repeat the process. Maybe iy is rather unusual with repeated attempts of netlist imports, but when double-checking lab teaching material, you do the same steps several times + screen dumps :-) 3. PDK resistor, value: I use the sky130_fd_pr__res_xhigh_po_0p3 in a simple circuit. The resistor seems to be limited to W=0.35 and L>0.50 in magic (but not in xschem). But the shown value in magic for the pcell (3.939k for a 0.5/0.35 sq resistor) is different from the value in xschem (2.857k for the same dimensions, which seems to be correct). Of course there are additional resistances in the connections but >1k is not realistic. Is the PDK correct and synced betwen electrical models and layout models? (My setup is using the latest versions of tools and PDK from ~Dec 2023.) Grateful for comments on the above questions!

You can also post messages to #magic for magic-specific questions, but here is fine, too. I monitor many of the channels. (1) I once had an idea that if I kept the snap spacing at 2x the minimum manufacturing grid, then I wouldn't run into problems with the centers of things like wires and contacts being at 1/2 grid points. A long time later, and I find that the first thing I do when I start magic is

snap int

(short for

snap internal

), which gets me on the 5nm grid. Probably the .magicrc file should just set it that way, and then it would stop being an issue. You can actually move things on the internal grid spacing even when the snap is set higher.

move e 1

will move east by one snap position, but

move e 1i

will move east one internal unit, ignoring the snap. (Likewise,

move e 5nm

will do the same.) (2) I will need to check this, and an example would be helpful. The "import spice" script is supposed to be re-entrant; that is, you are supposed to be able to read it on top of an existing layout and it should figure out if there are missing devices, and add them, or different port names, and change them, leaving anything else alone. So that's not working as advertised. (3) There are five characterized widths of resistor devices in sky130; W=0.35um is the narrowest of them (the five widths correspond to an exact number of contacts fitting the width at the terminals with minimum spacing between). Magic enforces L > 0.5um mainly because resistor models become very inaccurate unless L >> W. I could have gone with a reasonable rule of thumb like L > 5*W but I didn't want to be anal retentive about it. As far as the resistor value: Yes, xschem is giving the value based on sheet rho, while magic is including the terminals. For the terminals, I am not sure where I got the expression I'm using, which is (188 / W), which comes to 537 ohms, but the res_xhigh_po model has a more complicated expression

-46.62/(w*w)+331.73/w+20.576

which comes to 587 ohms. That seems quite high to me, too, although I've seen explanations about how the titanium nitride makes very poor contacts. The standard value for poly contacts is given in the documentation as 152 ohms, but that's for the standard square via cut, and the via for the resistors is very long. It seems reasonable to expect that the long via would have a lower resistance than a single minimum-size square via. But that's the equation that's in the characterized model. You can find the exact value by simulation; any value given by either xschem or magic is only a guideline, since the device is parameterized only by W and L.

Tim, thanks for very good and detailed answers. 1. I recognize the 1/2 grid problem, which could be stressful close to a tape-out 🙂 Now I know the background and how to move things just a grid point if necessary. 2. I will provide you with a simple example, let me come back on this. 3. The contact resistance from metal to actual resistor is higher than I expected. Really good to know the background, why the difference, and what value to trust. (In the beginning of my carrier, I did a lot of test structures and measurement for contact resistances since the group worked on metal-silicide-Si barriers, so I know it can be trickier with real structures than the schematic indicates...)

What is the course link? It is open?

Sorry, not open.