Hey there ! Our paper on High-Level Synthesis Driven ASIP Design Automation Tool for RISC-V Microprocessors is now published. We are automating the OpenASIP flow with Vitis HLS https://ieeexplore.ieee.org/document/10416066 Project uses a tcl script and a docker image. You can see the files here: https://github.com/DELTAICLAB/DELTA-V