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PDK <says> the spice models are only valid when VG...
# analog-design
l
PDK says the spice models are only valid when VGS >= 0. Will my family be cursed if I have a small negative gate voltage like V_G = V_S - 0.2 or something, or should I expect stuff to be reasonable and fine?
u
I expect garbage in garbage out type of philosophy…
l
The model will work outside of these ranges. But you really want to use MOS with VGS < 0, you should use the varactors, that are better modeled for this region. Just remember that the mosfet are symetrical devices. The drain and the source terminals are interchangeable.
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l
How should I turn an NFET deeply off, as off as possible?
I'm trying to minimize current leaking from my cap through my NFET when it's off. As you can see, the cap doesn't last long. I don't want to anger the gods with negative VGS though...
l
The trick is not just have VGS < 0, but VDS = 0. It is not a problem for our open source PDKs, as leakage is large only for more advanced nodes. But if you need it, implement a T switch https://www.sciencedirect.com/science/article/abs/pii/S0026269217306924
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l
I have a gajillion of these, so I probably can't use something so big. But it's a starting point. Thank you.
Will also try to understand the varactors
u
Also, maybe move to HVT
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l
Oh yes I got slight improvement with pfet hvt. forgot to include in picture.
l
l
Thanks! For future thread readers:
Those slanty lines connect where they point right?
l
Nope. Those are connections to the supply voltage. This article shows that you can reduce the leakage by connecting the bulk terminal to a reference voltage. There is leakage in in the parasitic diodes formed in the pn junctions between the drain/source terminals to the bulk, even if they are reverse biased.
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l
You just saved me much pain. I have not seen this notation before.
I can't seem to get below 200fA leakage (when ranging v(t1) between v(t2) + 0.2v and v(t2) - 0.2v) for this switch no matter what transistors I use or what I set b, phi, or ref. Any idea what I'm doing wrong?
l
Where are ref and b nodes connected to?
l
Voltage sources. I tried all kinds of ranges. With this particular setup in the screenshot I have v(phi)=-2.4, v(ref)=-0.8, v(b)=-1.5
That's what minimizes i(t1) I mean.
Looks like that was it. Well that was 3 days hahaha
l
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l
Wow just 1 transistor
l
See, this is a switch testbench. VB = 2.5, VDD = ENB = 5 V, and 0 < VA < 5.0
As you can see, even for a gmin of 1e-21, the minimum current the model can reach is about 1 fA
l
What are those elements on the right? It causes a dc sim to happen?
l
I'm setting the transistor input voltage and the supply voltage VDD with those voltage sources. I prefer this way. The boxes above are spice code to run the sim
See for yourself. This is the beauty of open source.
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l
So if I'm understanding correctly: Transistor spice models basically breakdown under 1fA of current, so I can't properly sim/test the switch?
l
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Now, a complementary switch, which is a bit more useful. Depending on the input voltage, there is parasitic currents for VA < VB
l
Mm I was getting same result as you before but now different
l
If you change the models to ff and temperature to 125 C, this happens
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That is crazy. Your results should be the same as mine. Your models must be different
l
Now I'm questioning everything
l
You're using two PMOS devics
l
brainfart
Getting same as you
l
Then, now you have a good testbench. You should do something with your other design. Make a voltage source for all signals
l
Any results under a few fA will be meaningless right?
l
Remember that, propably, a design with this technology would have a single supply of 5 V and a ground. I think the designs manufactured have a core supply of 1.8 V and another of 3.3 V. These should be the limits of your signals.
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Yep, because the models can't see it. But 1 fA is crazy low. If you have a 1 pF cap, with 1 V on it, it would take... 1k seconds to discharge it completely, I think. I'm not that good with calculations
The problem arises for higher temperatures and some corners. All depends on your application.
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l
a 1x1um cap is 3fF according to the models. I was hoping to fit in millions of caps in my 10mm^2 for chipignite. But seems I'll have to go for bigger + fewer caps if I want to rely on the spice models in any meaningful way (which of course I must). I will live
l
You do know that if you connect it to the pads, there will be leakage also, don't you?
l
Yes although my understanding beyond that is very limited
l
Not to say that, chipIgnite is quite cheap to get, compared to TSMC 2 nm, but it would be a very expensive capactior!
l
I don't understand
You mean the whole chip would just be a big capacitor?
l
Nor do I understand what you want to accomplish. A big switch and a big cap in a chip Ignite run? What do you want to design after all? And, this is not a chat window and we are polluting the thread. And it is very late here for an old grumpy man in Portugal. Time to go.
l
Oh sorry! Thanks for all your help!
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