If I use the following code : always_latch begin if (en_out) begin display = ac[7:0]; end end …the synthesis step fails with the following message [ERROR]: Synthesis failed. There are unmapped cells after synthesis. [ERROR]: Step 1 (synthesis) failed with error: -code 1 -level 0 -errorcode NONE -errorinfo { while executing "throw_error" (procedure "check_unmapped_cells" line 7) invoked from within "check_unmapped_cells $final_stat_file" (procedure "run_synthesis" line 35) invoked from within "run_synthesis"} -errorline 1 If the above code is changed to : assign display = en_out ? ac[7:0] : display; ... openlane has no issue. How latches are handled in openlane? Is it fine to use latch?

check this path

set ::env(SYNTH_LATCH_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/latch_map.v"

Thanks @Vijayan Krishnan. This file present in sky130 but not in gf180. But I have got the idea. I will create the file for gf180 and use.