https://open-source-silicon.dev
Join Slack
That shouldn't be a problem, I'm just saying to keep the previous value. It does work in simulation ...
# openlane
f
That shouldn't be a problem, I'm just saying to keep the previous value. It does work in simulation I also googled around a bit for this and have found some more stuff. As far as I can tell, yosys doesn't natively support clock gating, however, there is a plugin for it that does exactly what I want https://github.com/AUCOHL/Lighter I managed to get it installed in the container and by putting it in the big block of yosys commands in 
synth.tcl
Copy code
tee -o "$::env(synth_report_prefix)_pre_synth.$CHK_EXT" check
opt_expr
if { $::env(SYNTH_NO_FLAT) != 1 } {
    flatten
}

plugin -i cg_plugin.so
plugin -l
yosys -import
reg_clock_gating sky130_fd_sc_hd_ff_map.v


opt_expr
opt_clean
opt -nodffe -nosdff
fsm
it does seem to replace things with the right gate, however, yosys then errors out saying there is no 
\sky130_fd_sc_hd__dlclkp_2
in the design:
Copy code
Module `\sky130_fd_sc_hd__dlclkp_2' referenced in module `\spade_top' in cell `$auto$<http://ff.cc:266:slice$100.genblk3.genblk1.clk_gate|ff.cc:266:slice$100.genblk3.genblk1.clk_gate>' is not part of the design.
Placing it later solves the error but does not do the replaceement. Looking into the PDK, I have found the cell definition at https://github.com/efabless/skywater-pdk-libs-sky130_fd_sc_hd/tree/master/cells/dlclkp However, in my local setup, yosys seems to look for cells in 
/home/frans/.volare/volare/sky130/versions/cd1748bb197f9b7af62a54507de6624e30363943/sky130B/libs.tech/openlane/sky130_fd_sc_hd
And there there is a 
no_synth.cells
which contains the clock gated cell, so I'm not sure what to make of that. Is the cell in 
no_synth.cells
because it is broken, or because it isn't expected to be used?
d
Not expected to be used. We've unfortunately neglected to document why each cell is excluded like 4 years ago when we created that file- some are excluded simply because Yosys wasn't (and as far as I know still isn't) able to handle cells with multiple outputs, for example. I'll track this issue here: https://github.com/RTimothyEdwards/open_pdks/issues/430 The cells that are known bad and cannot be manufactured however are in 
drc_exclude.cells
. Do not use those. 
dlclkp_2
should be fine.
f
Cool, thanks!
Back to playing with this. While I got it to pass through synthesis by adding a verilog file with the black box from Lighter, it now fails later, usually during global routing with
Copy code
OpenROAD 75f2f325b7a42e56a92404f33af8e96530d9b202 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO]: Reading ODB at '/openlane/designs/spade_top/runs/build/tmp/17-spade_top.odb'…
define_corners Typical
read_liberty -corner Typical /home/frans/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
Using 1e-12 for capacitance...
Using 1e+03 for resistance...
Using 1e-09 for time...
Using 1e+00 for voltage...
Using 1e-03 for current...
Using 1e-09 for power...
Using 1e-06 for distance...
Reading design constraints file at '/openlane/scripts/base.sdc'…
[INFO]: Setting output delay to: 2.0
[INFO]: Setting input delay to: 2.0
[INFO]: Setting load to: 0.033442
[INFO]: Setting clock uncertainty to: 0.25
[INFO]: Setting clock transition to: 0.15
[INFO]: Setting timing derate to: 5.0 %
[INFO]: Setting signal min routing layer to: met1 and clock min routing layer to met1. 
[INFO]: Setting signal max routing layer to: met5 and clock max routing layer to met5. 
-congestion_iterations 50 -verbose -congestion_report_file /openlane/designs/spade_top/runs/build/tmp/routing/groute-congestion.rpt
[INFO GRT-0020] Min routing layer: met1
[INFO GRT-0021] Max routing layer: met5
[INFO GRT-0022] Global adjustment: 30%
[INFO GRT-0023] Grid origin: (0, 0)
[INFO GRT-0043] No OR_DEFAULT vias defined.
[INFO GRT-0088] Layer li1     Track-Pitch = 0.4600  line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met1    Track-Pitch = 0.3400  line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met2    Track-Pitch = 0.4600  line-2-Via Pitch: 0.3500
[INFO GRT-0088] Layer met3    Track-Pitch = 0.6800  line-2-Via Pitch: 0.6150
[INFO GRT-0088] Layer met4    Track-Pitch = 0.9200  line-2-Via Pitch: 1.0400
[INFO GRT-0088] Layer met5    Track-Pitch = 3.4000  line-2-Via Pitch: 3.1100
[INFO GRT-0019] Found 418 clock nets.
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0003] Macros: 0
[INFO GRT-0004] Blockages: 12600

[INFO GRT-0053] Routing resources analysis:
          Routing      Original      Derated      Resource
Layer     Direction    Resources     Resources    Reduction (%)
---------------------------------------------------------------
li1        Vertical            0             0          0.00%
met1       Horizontal      22008         10218          53.57%
met2       Vertical        16792         10805          35.65%
met3       Horizontal      10988          7272          33.82%
met4       Vertical         6812          3366          50.59%
met5       Horizontal       2172           899          58.61%
---------------------------------------------------------------

[INFO GRT-0101] Running extra iterations to remove overflow.
[INFO GRT-0197] Via related to pin nodes: 7896
[INFO GRT-0198] Via related Steiner nodes: 75
[INFO GRT-0199] Via filling finished.
[INFO GRT-0111] Final number of vias: 10043
[INFO GRT-0112] Final usage 3D: 46324

[INFO GRT-0096] Final congestion report:
Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
li1                  0             0            0.00%             0 /  0 /  0
met1             10218          4670           45.70%             0 /  0 /  0
met2             10805          6852           63.42%             0 /  0 /  0
met3              7272          2301           31.64%             0 /  0 /  0
met4              3366          2229           66.22%             0 /  0 /  0
met5               899           143           15.91%             0 /  0 /  0
---------------------------------------------------------------------------------------
Total            32560         16195           49.74%             0 /  0 /  0

[INFO GRT-0018] Total wirelength: 146700 um
[INFO GRT-0014] Routed nets: 2264
[INFO GRT-0006] Repairing antennas, iteration 1.
[INFO GRT-0043] No OR_DEFAULT vias defined.
[INFO GRT-0012] Found 149 antenna violations.
[INFO GRT-0015] Inserted 191 diodes.
[INFO GRT-0054] Using detailed placer to place 17 diodes.
[INFO GRT-0009] rerouting 1878 nets.
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 17
[ERROR GRT-0232] Routing congestion too high. Check the congestion heatmap in the GUI.
Error: repair_antennas.tcl, 19 GRT-0232
Checking the GUI, the routing congestion is indeed much much higher than it was before doing this. My uneducated guess is that this is because I now have 100 different clocks that are routed separately, is that possible? And is there anything I can do to avoid that problem?
u
Wondering how CTS is handling this, what is the average loading on your ICGs?
f
Where do I find that info? Is it shown in the cts.log or a step before? The CTS log is unsurprisingly quite long, 4000 lines but a quick search doesn't show any average load number
7 Views
Open in Slack
PreviousNext
Powered by

What is Linen?

Linen is a search-engine friendly community platform. We offer integrations with existing Slack/Discord communities and make those conversations Google-searchable.

Powered by