I am doing some experimentation with fine grained clock gating and would love to use the openlane flow to test it out. However, I can't find much info about how well supported clock gating is. I tried synthesizing a bunch of registers with a synchronous enable signal, essentially this:

wire ena;
wire[8:0] data;
wire ena_reg;
wire[8:0] data_reg;
always @(posedge clk) begin
    ena_reg <= ena;
end
always @(posedge clk) begin
    if (ena) begin
        data_reg <= data;
    end else begin
        data_reg <= data_reg;
    end
end

Synthesizing this with the default

flow.tcl

generates multiplexers to select the next value, which is not what I want. I have tried the same thing on ice40 FPGAs using yosys and there it correctly does "clock gating" (it uses the enable pins on the registers) Is clock gating like this even supported by openlane? Do I have to turn it on somehow? From searching around I've found that there is a clock gating cell:

sky130_fd_sc_hd__dlclkp_1

but I have no idea how I'd begin to try and use that

https://github.com/AUCOHL/Lighter claims to support this style in yosys. @donn is this in OL?

It's in OL2 which should be available soon™, but Frans already managed to install it in the OL1 container so that's cool

Yep, I should probably document how I got that working so 🤔 (because I will forget next time I poke around with this)