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<@U016EM8L91B> While working through your excellen...
# magic
y
@Tim Edwards While working through your excellent analog layout tutorial, I encountered an LVS error related to pin matching. Despite the two netlists appearing to have the same pin order, this issue arose. Why did this happen?
m
@Yusuke Sakemi I’ve seen this error before when the layout pin is not connected to the actual devices. Try looking at the device connections for 
ADJ
in both netlists.
y
Thanks for reply! I am going to check this.
@Mitch Bailey I have checked that the AJD pin was connected to devices in both netlists. Do you have any ideas for solving this issue?
t
@Yusuke Sakemi: That was from a relatively old version of magic. Can you please try updating magic and netgen first? If that doesn't solve the issue, then please post the two netlists (as opposed to just screenshots).
m
@Yusuke Sakemi it looks like the pcells are not extracting correctly. They do not have text assigned to the ports and sometimes this happens. I always run LVS on the gds and use the flatglob command to flattened cells without text before extracting. In your extracted 
zero_opamp
, 
ADJ
is connected to the second terminal of both 
M8
and 
M9
. However, the nfet subckt shown has the gate terminal 
a_n800_n138#
as the first terminal.
y
@Mitch Bailey Thanks for checking my netlist. The port order of an NFET or PFET is like this: drain -> gate -> source -> back gate. So, I think that the position of ADJ in the extracted netlist is correct. However, in the extracted netlist, G1 is located at the back gate, while it is located at the drain in the xschem netlist. So, as you pointed out, the netlist extraction is not working correctly. I think I need to update Magic and Netgen as @Tim Edwards suggested. Is there a tutorial for doing LVS that uses "gds flatglob"?
m
The port order for mos devices and primitive mos ‘X’ devices is drain, gate, source, bulk. You are correct. You can see this in 
X0
of 
sky130_fd_pr__nfet_01v8_lvt_FMHZDY
However, when you use pcells, the pcell subcircuit does not necessarily have the ports in that order. In subckt 
sky130_fd_pr__nfet_1v8_lvt_FMHZDY
, the port order is gate, bulk, source, drain.
You can use these command to extract a gds file with 
flatglob
flattening pcells.
Copy code
drc off
gds drccheck off
gds flatglob *__nfet*[A-Z]*
gds flatglob *__pfet*[A-Z]*
gds flatten yes
gds read zero_opamp.gds

load zero_opamp
extract no all
extract do aliases
extract do local
extract unique
extract

ext2spice lvs
ext2spice -o zero_opamp.ext.spice zero_opamp.ext
feedback save $zero_opamp-ext2gds.spice.feedback.txt
y
@Mitch Bailey Thank you very much! I did not know that the PCell pin order was not the same as the MOS model, thanks. Before updating software, I am going to try LVS using flatglob. I will report the results soon.
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@Mitch Bailey Do I need to run "gds write zero_opamp.gds" before running "gds read zero_opamp.gds"?
m
@Yusuke Sakemi You’ll need to create the gds file. I wouldn’t do it in the same magic session though, because you don’t want to mistakenly overwrite your mag data with the gds data.
Copy code
1. Create the gds data and quit magic.
2. Open magic and extract the gds file without saving the cells and quit magic.
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y
@Mitch Bailey Is this the full correct code that you mean ?
Copy code
(terminal) magic zero_opamp.mag
drc off
gds drccheck off
gds flatglob *__nfet*[A-Z]*
gds flatglob *__pfet*[A-Z]*
gds flatten yes
gds write zero_opamp.gds
** quit magic without saving cells **

(terminal) magic zero_opamp.mag
gds read zero_opamp.gds
load zero_opamp
extract no all
extract do aliases
extract do local
extract unique
extract

ext2spice lvs
ext2spice -o zero_opamp.ext.spice zero_opamp.ext
feedback save $zero_opamp-ext2gds.spice.feedback.txt 
** quit magic without saving cells**
m
Copy code
(terminal) magic zero_opamp.mag
gds write zero_opamp.gds
** quit magic without saving cells **

(terminal) magic zero_opamp.mag
drc off
gds drccheck off
gds flatglob *__nfet*[A-Z]*
gds flatglob *__pfet*[A-Z]*
gds flatten yes
gds read zero_opamp.gds
load zero_opamp
extract no all
extract do aliases
extract do local
extract unique
extract

ext2spice lvs
ext2spice -o zero_opamp.ext.spice zero_opamp.ext
feedback save $zero_opamp-ext2gds.spice.feedback.txt 
** quit magic without saving cells**
y
@Mitch Bailey @Tim Edwards I found out that the 'top level cell failed pin matching' error originates from Netgen. I performed LVS using two SPICE files from Tim's GitHub (https://github.com/RTimothyEdwards/tutorial_layout), but encountered the same error. After updating Netgen from version 1.5.244 to 1.5.268, the error disappeared. Thank you very much for your help. I've realized the importance of keeping software updated. (I updated Magic (8.3.363->8.3.460) as well; its palette list is fantastic!)"
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🌏 1
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