Hay I have done the post-simulation of the 7segment display for the magic file I have from Openlane. Although the post-simulation ran successfully,the output waves are very random. However,I tried to check whether power is working or not adding a xor in the spice file,it worked fine. So it should not have any issue with power supply.I have attached the Spice and testbench files.Please help me out.

What do you mean by random, do you have waveform of what you get and what you want? netlist is huge, difficult to make a suggestion blindly. Is this created from RTL? Does RTL sim passes? Maybe I’m missing context…

Yes,magic is created from RTL using openlane carevel user_proj_example.Yes it passes prelayout simulation.Here is the waveform

It looks like you expect signal change around 350us, but you only simulated 3uS on spice. Also, is this the recommended validation, is it possible to run GL sim and/or GL+SDF ?

No it is simulated 13.8 us.Earlier we simulated for 376 us.It had same result.For now, we tried to force the initial outputs to check whether it works or not.It is all same....I did not try that one.Do u know any tutorial for GL+ SDF verification one so that I can follow for mine?

I see, thanks for clarifying, I think clock is fine. If you really want to debug this, I suggest you try to narrow it down, some ideas... • Is clock signal reaching your flops? Try following the clock line. • Is your stimulus propagating through combo cells? Are inverters inverting? • Maybe pick something closer to the inputs instead top level output or pick an intermediate timing path.

Hay ,I tried couple of thing . 1.I tried to design a simple inverter following this guide.https://openlane.readthedocs.io/en/latest/usage/designs.html .Then tried post simulation .It worked perfectly. 2.Used caravel user_proj_example to design same inverter.The magic file did not work for post lay out simulation.Whenever, I tried to ext2spice for the magic,it just automatically exited the whole magic file. Howver,could you please give me any tutorial to follow in order to do GL ,GL+SDF verification ?

Want to post the netlist and tb for the inverter showing the issue? I don’t have any tutorials, not sure what is supported by open source flow.

I did not run the testbench .I will just run now and will share the output