Hi, I'm trying to use the fet pcells from a klayout script, but it generates S D and G metal1 connectors with 0.002u extra in the height, causing DRC offgrid errors. This happens for the pfet, nfet and nfet_06v0_nvt pcell classes. The shared script has more comments inside. I've already made some klayout scripts using the vias and resistor pcells and only with the fet ones this errors are happening.