Hello, all. When I make a cell and check LVS, there is an warning about "must-connect". but, after I instantiate the cell I made into another upper cell, there is an error as below. I set VSS as substrate name. Should I change the substrate name? or do something for this?

@Junbeom Park Do you still get the error with a psubstrate tap to VSS?

Yes. To check my configuration, I tested LVS with simple inverter design as below. Though I used bulk tied PMOS and NMOS to make inveter, there is still an error related with must-connect.

@Junbeom Park to be honest, I’m not sure what the best solution is to the problem. I wonder if it has anything to do with the substrate definition in

lvs/rule_decks/layers_definitions.lvs

#=== BULK LAYER ===
sub = polygon_layer

You might try changing this to

#=== BULK LAYER ===
sub = extent

@Mitch Bailey it works well. Thanks for your help