It's hard to find the examples (needles in a haystack), but it occurs to me that I have standard cells I designed which have been integrated into the flow. They are just decap and fill cells in open_pdks (sky130/custom/sky130_fd_sc_hd/gds/). I can give you the general run-down, though, while I continue to try to track down the several projects that I know implemented custom standard cells (the one that immediately comes to mind was a transmission gate, but I'm having difficulty recalling what project that was part of).
For starters, you want to look carefully at one of the sky130 standard cells and note how each cell has certain layers (diffusion, n+, p+, nitride poly cut) that extend to both sides of every cell and match heights so that they form a continuous strip across the abutment between two neighboring cells. Also note the route pitch of the standard cell set, which is in the technology LEF file. The local interconnect for any pin should be centered on a routing grid point and be large enough to place an "mcon" contact without causing any DRC violations. The cell width (according to the abutment box) must be a multiple of the unit cell as defined in the technology LEF file. The cell will need views in at least GDS, LEF, and verilog, and will need a .lib file entry which is preferably well-characterized for timing, but can also be fairly "boilerplate" with timing values sane enough to keep the synthesis tools from doing stupid things with it.
I have less experience with how to fold it into openlane, but there are variables for things like "EXTRA_LEFS" (might not be the exact name) where you can add in extra libraries. You can either add in your standard cell by instantiating it directly into verilog; although if it implements a general operation that can map to a function in yosys, there is a way to tell yosys what that mapping is. If I know what you have in mind I can be a bit more specific.