How much should I trust zero_opamp & bandgap_opamp from the sky130_tests? Think I can use them out of the box? What's the difference between them? Is the ADJ pin for offset voltage? Should I grab an op-amp from some other repo (maybe this one?) I guess this question is for @Stefan Schippers since he's the author of the schematic.

This opamp is used in self calibrating circuits, where the ADJ input is used to cancel the input offset in a first time step, then the ADJ level is stored into sample capacitor and with this setting the compare is done. The opamp works well in simulation, however not tested on silicon. With a simple metal option (or some small disable logic) you can disable the ADJust function and turn the opamp into a normal OTA. Same thing for the following gain_stage. The input stage of the OTA is with p-FET, so + and - input levels must be sufficiently below VCC to turn on these

pfet_01v8_lvt

transistors. If you need the opamp for different input dynamic range you may consider a nfet input stage or a rail to rail (nfet + pfet) stage.

Sorry you're talking about zero_opamp.sch or bandgap_opamp.sch? What's the difference between them?

The bandgap uses two comparators. Bandgap voltage regulation is done with

bandgap_opamp

, this Opamp has an offset compensation input (ADJ). This adjustments is done with a secondary OTA,

zero_opamp

. This secondary OTA in a first phase cancels out its own offset, then it cancels out the bandgap offset. This setup has the advantage that the primary

bandgap_opamp

is never disconnected from the control loop. Some other offset cancellation techiques use different approaches, like chopping (swapping inputs / outputs) but this causes some switching noise so a LPF filtering is probably needed. The

tb_bandgap_opamp

is just a testbench for testing the

zero_opamp

OTA (followed by a gain stage) used to sense a 1mV input differential signal. This would be impossible without some offset cancellation, since mos transistor mismatches yield differential input equivalent offsets in the range of 8-15mV even if using big and matched transistors. See the attached short pdf for some background (it's a 24 year old doc, so may be little outdated, schematics were already drawn with xschem though 😄).