How can I make behavioral model for SAR ADC components (comparators , some logic gates , ..... ) using open source tools ?🤔

Generally, what I do is to make a pure verilog model but with "real" valued inputs or outputs, which can then be used in simple assignment equations. This does not capture any of the complexity of the device but it can be used for quick functional testing inside a larger system like an SoC. This method can run into occasional complications. I once had a current bias generator and was combining two outputs to double the current. But as far as the verilog simulator was concerned, I was connecting two outputs together, which is forbidden; there is a way to do this in System Verilog, but I don't think iverilog supports any of that syntax.