Hello I am trying to make a post layout simulation for the magic file of 7 segment display from opnelane/user_proj_example/runs/user_proj_example/results/final/mag using NGSPICE.I am having this issue when trying to make the Xschem testbench.Please help me out.

Really, you don't want to try to simulate a synthesized digital circuit with ngspice, although a 7 segment display driver might be small enough to do successfully. Regardless, you do have to include all the model files. It looks like you included the spice library of the standard cells, but not the low-level device models. The easiest way to do that in xschem is to use the "corner_tt" symbol.

Thank you for your reply.Could you please tell me whether there is any option to do post layout simulation in openlane?

You would need to ask the openlane developers. I know that the main block to post-layout simulation is the lack of backannotation in iverilog. There is a freeware/non-open-source tool "cvc" by Tachyon Design Automation (http://www.tachyon-da.com) that can do it; I'm not sure how to set that up with openlane, though.