while add my design i am facing this Error . can any one help me to resolve it ????

What’s in your

linter.log

?

i don't lknow

The name of the log on your machine is in the last line before the first error: ../m/home/intern....../logs/synthesis/linter.log

How to debug it ??

You have to read that file and see what it says. This kind of problem usually happens when your SystemVerilog file uses some feature that Yosys doesn't support. At the very least the linter.log file should indicate which of your source files (if you have more than one) is causing the problem