Hi @Mitch Bailey, this is the error that I mentioned during the meeting. It's during the LVS phase for a D_FF circuit. The DRC is ok but I when I run the LVS, it's highlighting errors at the input D, and the biases VDDD and VSSD. When I check the D input error, i can't identify the issue, the D input is connected to a tgate with two transistors. I used the "Trace All Nets" tool to identify where is the error but it seems it is ok. Please find attached the photos of schematic of the D flip flop, the layout, the LVS error, and the D highlighted with the "Trace All Nets" tool. The configuration that I am using for the LVS phase is: • Substrate name: VSSD • Run mode: flat • variant options: D • I set the netlist path where my .spice schematic file is placed • Check for the "SPICE net name" and "Top level pins" options Also find attached the .gds and the .spice files. Please let me know your thoughts, I truly appreciate your willingness to help.

@Juan Sebastian Moya I don’t see any obvious errors. I’ll take a look at the rule files in the morning.

Thanks!

@Juan Sebastian Moya The LVS that I ran passed, but I modified the rule file to extract a psubstrate layer and I may not be using all the options that you have set. Do you run an LVS script or is there a GUI interface? Could you share the details?

Hi @Mitch Bailey, I am using a GUI interface. The LVS configuration that I use is: Substrate name: VSSD Run mode: flat variant options: D I set the netlist path where my .spice schematic file is placed Check for the "SPICE net name" and "Top level pins" options That's all I am using for my setup. Any additional information of my setup that you need?

@Juan Sebastian Moya Sorry for the delay. I installed the GUI and used the same options, but I still get a clean LVS result. Are your rules up to date?

Hi @Mitch Bailey, I have the last 2023 version. I got this error from last year. I saw that the volare version was update in the second week of 2024. I will check with the last version. I will keep you posted. Thanks for the help!

Looks like I’m using the same options as you.

Substrate name: VSSD
 Run mode: flat
 variant options: D
 I set the netlist path where my .spice schematic file is placed
 Check for the "SPICE net name" and "Top level pins" options

I’m using klayout version 0.28.15

Hi @Mitch Bailey, I updated my klayout version (I had the 0.28.12) and LVS passed. Thanks so much for the help.