Hello ,I am trying to design 7 segment display .I have used 8 to 14 io pin.And changed pin_order.cfg in openlane/user_proj_example, deleted all pins but only used io pins and clk and reset pin .It is throwing error for the pins.

The verilog file uses

wb_clk_i

,

wb_rst_i

,

io_oeb[6:0]

and

led_out[6:0]

. Can you try erasing all other pins from the

pin_order.cfg

file?

Thank you for your reply.after doing so,it still throwed error about mismatching io_out[6:0] and io_oeb[6:0].I did not use those pins though.Now I added those pins in my pin_order.cfg along with my used pins I.e. io_oeb[148],io out[148] .