Hi, I'm trying to port the waffle transistor from sky130 to gf180mcu. This transistor is composed by 10 different frames that are arranged into the waffle topology. Until now, some of the frames i've ported has "NPLUS COMP islands inside PPLUS COMP regions". The original ones doesn't have them separated, but DRC is not giving me any warning in the ported version. I don't know if this layout is better, the same, or if is going to destroy the chip. @Tim Edwards @Boris Murmann

You should not have overlapping NPLUS and PPLUS. This should not be substantially different from the sky130 layout; while sky130 separates the "DIFF" and "TAP" layers, the NSDM and PSDM layers still have to be present, and likewise cannot overlap.

I've observed in DRC reports that implanted zones should not overlap, However, I´m not sure if it is advisable to have a separation between COMP boxes when they contain different implants. When implants don't overlap, DRC passes both with and without this separation.

COMP with no separation but with NPLUS on one side and PPLUS on the other is an abutted tap structure. It is generally legal in most foundry processes and will save space vs. isolated COMP regions. It only works, of course, on the side of a FET that is attached to power or ground and shares the same net as the tap.

Thanks a lot Tim