"Hello, I have designed a circuit a 1T1R structure, and I am exploring ways to increase the number of levels for storing multiple bits for 1 single cell. In my schematic, I have implemented a 1T1R (1 Transistor, 1 Resistor) configuration. I am considering using a series of pulses during programming, alternating between SET and RESET operations while maintaining a gap with a reference 3 resistors how should be done. or Specifically, I plan to repeat the sequence RESET, SET, GAP (maintaining 0V) three times. Would this approach effectively enable the storage of multiple bits in the cell, and do you have any suggestions for improving this strategy?"@Akash Levy @Mitch Bailey

Don’t have any hands-on experience with simulation, but from what I understand of flash memory multi-bit storage, you’ll need 4 levels to store 2 bits and 8 levels to store 3 bits. With flash memory, the dual gate mosfet Vth is altered to correspond to the data values. With re-ram, you’ll need to define resistance ranges (with gaps) that correspond to the data values. I don’t know about the strategy of alternating RESET/SET. From the documentation, it looks like repeated SET or RESET are used until the desired resistance is achieved.

@Mitch Bailey thank you

i would use more than 3 reference resistors. you should use separate reference resistors for write and read