@Tim Edwards I have used digital cell

dfrtp_2  and2_2  inv_2

from standard cell library into my analog design. These cell lacks explicit power pins like

VCC , GND

. While I managed to simulate the circuit in xschem/ngspice, how can I proceed with layout without these power pins? Are layout of std. digital cells available to include in magic? If yes, where to find them and ensure proper connections, especially for the

VCC

,

GND

pins with other block layouts ?

If you start magic with the startup script included in the PDK, then it will automatically have the digital standard cells in the regular search path. You should only need to do

getcell sky130_fd_sc_hd__dfrtp_2

or use

Options-->Library Manager

to get it. The power and ground pins are clearly marked on the standard cell layouts.

@vks digital standard cells used in xschem have power pins, simply the power pins are not shown in the symbol but are set via attributes. There is a reason for that: • Avoid clobbering the design with power nets hooked up on every digital gate. • usually the whole digital part placed in a schematic has the same VCC/VSS connections, so having explicit pins in the symbols is a boring task, you need to assign the very same net names on every cell. Using attributes you can select all cells and with a single edit attributes set/change the power connections for all. Power pins assigned via attributes are no different than explicit pins, in the spice netlist every standard cell has all the pins including power pins.

Thank you both for respective clarifications. I hope there no special considerations required in either schematic or layout using digital standard cells for purpose of LVS. Can you please confirm that ? @Tim Edwards can you please clarify this point w.r.t. placement of digital cells inside analog layout in magic

"(1) Align all cells to the abutment boxes in the same way that a digital synthesis placement tool would"

?

@vks: All digital standard cells are designed to be placed in rows and abutted to each other; they are designed specifically to avoid all DRC errors if placed in that manner (which includes alternate rows being flipped top to bottom; any cell should be able to be flipped side to side). If you place them any other way, you may end up with DRC errors between the cells. Of course you can space them so far apart from each other that they can never interact to form DRC errors, but that's just bad layout.

Ok, got it. Can you please clarify LVS query. Hope no special requirements for clearing LVS of analog design containing standard cells in it.

@vks: Per Stefan's comment, you will need to have a

VSS

pin in your schematic, and ensure that the power and ground properties of the digital standard cells in the schematic have been set equal to the pin names

VCC

and

VSS

. Beyond that, the main consideration is that the schematic is not going to dump the netlist of the standard cells themselves, but will expect you to have an

.include

statement in your testbench to include the standard cell SPICE library. For LVS purposes, you should read the standard cell library into the netlist. That requires setting up a more complicated script than just doing (assuming netgen)

lvs <A> <B>

. Here's an example script I wrote yesterday:

# Run script for netgen LVS
#
# NOTE:  Assumes PDK_ROOT is set in the environment: $::env(PDK_ROOT).
# and PDK is set in the environment: $::env(PDK)
#
# Script reads IP for the HVL library from the PDK, then compares netlists.
# Assumes that netgen is called with cwd = the directory above this one.

set pdklib $::env(PDK_ROOT)/$::env(PDK)
set techlibs ${pdklib}/libs.tech
set reflibs ${pdklib}/libs.ref

set setupfile ${techlibs}/netgen/sky130A_setup.tcl
set hvlib ${reflibs}/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice

set circuit1 [readnet spice netlist/lvs/dac_3v_8bit.spice]
set circuit2 [readnet spice $hvlib]
readnet spice netlist/schem/dac_3v_8bit.spice $circuit2

lvs "$circuit1 dac_3v_8bit" "$circuit2 dac_3v_8bit" $setupfile \
        reports/dac_3v_8bit_comp.out

This has the same situation as what you're doing, which is to have a digital standard cell inside an analog layout. When multiple sources are needed for a netlist, you need to make multiple

readnet

calls to read in each file and attach them to a netlist specified by file descriptor ("$circuit1" and "$circuit2" in the script above). If I save the script above as, e.g.,

project_lvs_setup.tcl

, then I would run it through netgen using

netgen -batch source project_lvs_setup.tcl

.

@Tim Edwards Hello Tim, I was trying to get the script above working for a similar problem I am facing with my design that uses standard cells. I changed the script you posted above to the one below where my project folder contains folders for both schematics and layout.

set pdklib $::env(PDK_ROOT)/$::env(PDK)
set techlibs ${pdklib}/libs.tech
set reflibs ${pdklib}/libs.ref

set setupfile ${techlibs}/netgen/sky130A_setup.tcl
set hdlib ${reflibs}/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice

set circuit1 [readnet spice ~/project/mag/comparator.spice] #mylayout
set circuit2 [readnet spice $hdlib]
readnet spice ~/project/xschem/comparator.spice $circuit2 #myschematic

lvs "$circuit1 comparator" "$circuit2 comparator" $setupfile \ ~/project/lvs/comp.out

Where I use the following command prompt to compare the netlists:

netgen -batch /mag/comparator ~/project/stndcelllvs.tcl

When I do this, I get an invalid command name "/mag/comparator" as output. Could you help me with the way you created your script and what I might be doing incorrectly?

@Stijn van Himste: The only thing you're doing wrong is that

-batch

needs to be followed by a valid Tcl command, so what you need is

netgen -batch source ~/project/stndcellslvs.tcl

on the command line.

That works, thank you!