Hi everyone,I am trying to design a simple inverter.But I M getting this error.When checked the log file in synthesis,it says that the network is combinational.

I had a similar issue, what I did to resolve was including the default cases for all case statements I have in my code, but I also realized that all signals must be driven on each case so I added a statement initializing all of them at the beginning of the always block. Not sure if this will help or is the most recommended thing to do but it worked for me, hope it helps.