I would like to report a couple of problems I’ve encountered with passing precheck with GDS produced by KLayout ("PRIMARY_SIGNOFF_TOOL" : "klayout") in case somebody else will encounter them. • First problem was soft connection LVS check failing. It appeared that Klayout created two VDD and VSS labels, on M4 and on M5 ring stripes. This confused Magic LVS extraction and it created additional wires (VDD_uq0/VSS_uq0) which obviously broke Netgen comparison. • Second problem was failing CVC check. It turned out to be because of case sensitive spice to CDL conversion. VDD/VSS labels from KLayout were in capitals and it lead to CVC failing to find power lines as it searches “vdd” and “vss”. Both problems were trivial to fix with small KLayout script to modify labels, but I think it is easy to address them automatically during extraction in precheck. I could share KLayout script or create an issue on github with logs if needed.

@Egor Lukyanchenko Thanks for the report. Verilog is case-sensitive, SPICE is not. Currently, LVS is case-insensitive, while CVC/OEB is case-sensitive. I believe magic extracts case-insensitive - but only extracts one of the variants (It shouldn’t use both upper and lower case in the same subcircuit for the same signal). Currently, there is no check for possible conflicts. For your first point, are the M4 and M5 ring stripes with the same labels connected?

For your first point, are the M4 and M5 ring stripes with the same labels connected?

Yes, they are on VDD/VSS core rings vertical and horizontal stripes.