Hi everyone, i am currently working on GFMPW-1 Shuttle Program, when we harden our design with openlane by using "gf180mcuD" and other Standart Cell Library, is it obligatory to run the openlane with this config.json file , i mean am i free to change clock period , density ext ? { "PDK": "gf180mcuD", "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", "DESIGN_NAME": "user_proj_esc", "VERILOG_FILES": [ "dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_esc.v", ], "DESIGN_IS_CORE": 0, "CLOCK_PORT": "wb_clk_i", "CLOCK_PERIOD": "24.0", "FP_SIZING": "absolute", "DIE_AREA": "0 0 700 1000", "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", "PL_BASIC_PLACEMENT": 0, "PL_TARGET_DENSITY": 0.45, "FP_CORE_UTIL": 40, "MAX_FANOUT_CONSTRAINT": 4, "PL_RESIZER_MAX_WIRE_LENGTH" : 30, "CTS_CLK_MAX_WIRE_LENGTH" : 25, "RT_MAX_LAYER": "Metal4", "VDD_NETS": [ "vdd" ], "GND_NETS": [ "vss" ], "RUN_HEURISTIC_DIODE_INSERTION": 1, "RUN_CVC": 1, "QUIT_ON_LINTER_ERRORS": 0 }

yes, you can change as per requirement