@channel : Sorry for the channel blast, but we (at Efabless) are working on defining the "next generation" of Caravel, and need to define the pinout of the harness. There is ample room around the existing caravel/caravan/openframe padframe to roughly double the existing number of pads. However, the more pins there are, the larger the package and the more complex the development board. I do know that some designers had projects in mind which exceeded the 38 GPIOs available in the current Caravel chip, and some people have told me that they were reducing the scope of their designs to fit it in the existing 38 GPIOs. I would like to get some feedback from anyone who has considered a design that requires a large number of GPIO pins about what the use case is, and what is the minimum number of GPIOs needed for that use case. Are there any obvious use cases which would require more than 64 GPIOs?

A 32-bit processor will need more than 64 pins if it needs to access some GBs of ram outside.

kind of tangential, but having an (optional) boundary scan would be incredibly handy and would provide a lot of the value of the current caravel CPU but with much less logic

@Anish: We are planning DFT and are just waiting for a test chip to get back.

I am currently working on a ONFI compliant NAND Flash controller, which at the moment fits into Caravel, but additional DRAM access would be nice and would need additional pins.