Hi all, I'm getting an error when trying to run openlane on a simple version of the caravel_wrapper with the

user_project_wrapper.def

as a template. Openlane is failing at step 4 (IO placement) telling me that there are 416 IO pins (looks about right according to the verilog), but only 28 "positions" (not sure where this number 28 is coming from). If i look at the def. there 1134 lines with the word

PORT

on them so I have no idea why I'm getting this error. Can anyone offer any insight? Thanks in advance.

OpenROAD 6f9b2bb8b808b1bb5831d4525d868212ae50517a 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO]: Reading ODB at '/media/tom/Storage/Linux/repos/projects/openwave-caravel/openwave/cells/caravel/runs/RUN_2023.12.07_19.53.49/tmp/floorplan/3-initial_fp.odb'…
define_corners Typical
read_liberty -corner Typical /home/tom/repos/edalibs/pdks/gf180mcu/gf180mcuD/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib
Using 1e-12 for capacitance...
Using 1e+00 for resistance...
Using 1e-09 for time...
Using 1e+00 for voltage...
Using 1e-03 for current...
Using 1e-06 for power...
Using 1e-06 for distance...
Reading design constraints file at '/openlane/scripts/base.sdc'…
[INFO]: Setting output delay to: 8.0
[INFO]: Setting input delay to: 8.0
[INFO]: Setting load to: 0.07291
[INFO]: Setting clock uncertainty to: 0.25
[INFO]: Setting clock transition to: 0.15
[INFO]: Setting timing derate to: 5.0 %
Found 0 macro blocks.
[ERROR PPL-0024] Number of IO pins (416) exceeds maximum number of available positions (28).
Error: ioplacer.tcl, 51 PPL-0024

from my experience it usually meant that the die area was too small for all the pins to be allocated, so setting

"FP_SIZING": "absolute"

and

"DIE_AREA"

to something like

"0 0 200 200

(experiment with the values) may fix it

Thanks @Kristaps Jurkans. Seem to be getting much further now

@Tom Can you share your

config.json

file?

Hi @Mitch Bailey, sure!

{
  "DESIGN_NAME": "caravel",
  "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
  "VERILOG_FILES": [
    "dir::rtl/defines.v",
    "dir::rtl/caravel.v"
  ],
  "CLOCK_PORT": "wb_clk_i",
  "CLOCK_PERIOD": 40,
  "QUIT_ON_SYNTH_CHECKS": 0,
  "FP_PDN_CHECK_NODES": 0,
  "SYNTH_ELABORATE_ONLY": 1,
  "FP_DEF_TEMPLATE": "dir::mag/user_project_wrapper.def",
  "MAGIC_ZEROIZE_ORIGIN": 0,
  "FP_SIZING": "absolute",
  "DIE_AREA": "0 0 2980.2 2980.2",
  "CORE_AREA": "12 12 2968.2 2968.2",
  "RUN_CVC": 0,
  "UNIT": 2.4,
  "FP_IO_VEXTEND": "expr::2 * $UNIT",
  "FP_IO_HEXTEND": "expr::2 * $UNIT",
  "FP_IO_VLENGTH": "expr::$UNIT",
  "FP_IO_HLENGTH": "expr::$UNIT",
  "FP_IO_VTHICKNESS_MULT": 4,
  "FP_IO_HTHICKNESS_MULT": 4
}

I'm basically building it up slowly from the one in caravel for my own integration into the wrapper

1. Why is your design named

caravel

?

caravel

is the final top level with the

user_project_wrapper

integrated into

caravel_core

and combined with

chip_io

. Your top level should be

user_project_wrapper

. 2.

SYNTH_ELABORATE_ONLY

is set meaning that you only want to do wiring, but you have nothing to wire to if

caravel.v

is just a wrapper. 3. Although the placements will be overridden by `FP_DEF_TEMPLATE`M, maybe adding

"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",

reserves the space.

I have a folder called

cells

which contains a mixture or analog cells (for which there are LEF, GDS, and RTL views), and digital cells. one of the cells is called caravel, and contains the caravel_wapper DEF and skeleton RTL file which I coppied from the caravel repo. I will ultimately use this to generate my wrapper GDS file which will then go into the caravel padframe. I'm new to openlane so in an effort to learn the process I'm starting as simple as possible and running the flow on an empty design initially but to the template caravel wrapper DEF. Once I know what I'm doing I will use it to connect up my dtop, and atop cells which will probably just be an elaborate only operation