Glad to announce our RISC-V Microarchitectures, RTL Design and Verification course is now live! Contact to book - https://api.whatsapp.com/send/?phone=919817182494&text=Hi+vlsideepdive%2C+I+have+a+query&type=phone_number&app_absent=0 The course with video lectures of around 6 hours, goes deep, as that is vlsideepdive's commitment to our supporters. The course starts with concepts on RISCV fundamentals, Architectural State and Instruction Set, Microarchitectures, and Performance analysis of processors. Then it offers a hands-on journey through the design of an RV32 processor. Starting with a single-cycle model, we'll advance to a multi-cycle and then a pipelined architecture, incorporating custom extensions. Practical learning is a key focus, as we'll use Verilog for design and testbench development. The course also includes an in-depth review of the ibex open-source core by lowRISC, a Google initiative. Participants will gain insights into architectural and microarchitectural concepts, covering branch prediction, superscalar design, out-of-order execution, and multi-core/multi-threading technologies. This is an ideal course for those looking to deepen their understanding of modern processor design." We do have live webinars scheduled for it's sister courses RISC-V Processor Memory Systems - https://vlsideepdive.com/risc-v-processor-memory-systems/ RISC-V Embedded Systems and IOs - https://vlsideepdive.com/risc-v-embedded-systems-and-ios/ In addition to that metavlsi offers a RISC-V Ninja certification in collaboration with India Electronics and Semiconductor Association on Made in India board by CDACINDIA - https://www.metavlsi.com/riscv-ninjas So we have everything right here on RISC-V International you may be interested in!