Hi everyone!
I'm trying to integrate a large analo...
# openroadh
Haziq Rohail
12/02/2023, 9:39 PMHi everyone!
I'm trying to integrate a large analog macro with gsg pads into the user_project_wrapper. However, when it tries placing the macro, it gives the error that the macro is taller than any row (the macro class used in lef file in this case is CORE, and it's dimensions are 140 um x 400 um). I've tried adding some obstruction layers using GRT_OBS but that doesn't seem to do anything, and I've also tried changing the macro's class from CORE to BLOCK but then it fails while generating the PDN. Does anybody know what variables I need to change to make it go through multiple rows, and prevent PDN and other routing generation steps inside the macro's area? Any help would be appreciated. Thanks!
m
Mitch Bailey
12/02/2023, 11:05 PMuser_proj_example Copy code
MACRO user_proj_example
CLASS BLOCK ;
FOREIGN user_proj_example ;
ORIGIN 0.000 0.000 ;
SIZE 2800.000 BY 1760.000 ;h
Haziq Rohail
12/02/2023, 11:19 PMThank you for responding! When I try integrating user project example, that clears all the checks. So I figured I'll try setting up my macro in the same manner. However, when I use class BlOCK and try integrating my macro, It gives this error in the detailed routing stage. The error in runs/run/logs/routing/13-detailed.errors I see is:
Error: droute.tcl, 40 vector: M range check __n (which is 4) >= this->size() (which is 0)
I can't figure out what could be wrong here. Is it that my macro's size is too different? The first few lines of the lef are as follows:
MACRO RO_basic
CLASS BLOCK ;
FOREIGN RO_basic ;
ORIGIN 0.000 0.000 ;
SIZE 140.000 BY 400.000 ;
PIN VDD
DIRECTION INOUT ;
USE POWER ;
m
Mitch Bailey
12/03/2023, 6:09 AMSorry, no idea. Are you manually placing the macro?
h
Haziq Rohail
12/03/2023, 9:45 AMno, I'm trying to place it through the flow.
m
Mitch Bailey
12/03/2023, 11:01 AMI haven’t heard of people being able to place hard macros with the flow. It might be possible, but most designs use
Copy code
"MACRO_PLACEMENT_CFG": "dir::macro.cfg",marcro.cfgh
Haziq Rohail
12/03/2023, 7:05 PMYes, I am using that. Sorry for the confusion, I thought you meant if I was doing it in a GUI like magic/klayout. The placement that I'm trying to use is 700 700 N in the macro.cfg file.
m
Mitch Bailey
12/04/2023, 12:12 AMOk, this is just a guess, but maybe
Copy code
Error: droute.tcl, 40 vector::_M_range_check: __n (which is 4) >= this->size() (which is 0)PDKopenlane/user_project_wrapper/runs/user_project_wrapper/config.tclh
Haziq Rohail
12/04/2023, 1:10 AMI've attached it in this message. Hope it helps.
m
Mitch Bailey
12/04/2023, 1:25 AMI don’t see any obvious problems. Can you share your current
RO_basich
Haziq Rohail
12/04/2023, 1:28 AMSure. I'm sharing both lef and gds.
m
Mitch Bailey
12/04/2023, 1:46 AMProbably won’t make a difference, but you might try deleting the n/pwell and via sections of the lef file.
If there’s still an error could you share the full error message and not just the last line?
h
Haziq Rohail
12/04/2023, 1:53 AMShould I delete them from within magic, and modify the gds as well, or do I just manually remove them from lef?
Haziq Rohail
12/04/2023, 2:01 AMhaziq@Haziq:~/GFMPW_2023/WEST-1$ make user_project_wrapper
/bin/sh: 1: cd: can't cd to verilog/dv/cocotb
/bin/sh: 1: cd: can't cd to verilog/dv/cocotb
make -C openlane user_project_wrapper
make[1]: Entering directory '/home/haziq/GFMPW_2023/WEST-1/openlane'
# user_project_wrapper
mkdir -p ./user_project_wrapper/runs/23_12_03_20_59
rm -rf ./user_project_wrapper/runs/user_project_wrapper
ln -s $(realpath ./user_project_wrapper/runs/23_12_03_20_59) ./user_project_wrapper/runs/user_project_wrapper
docker run -it -u $(id -u $USER):$(id -g $USER) -v $(realpath /home/haziq/GFMPW_2023/WEST-1/..):$(realpath /home/haziq/GFMPW_2023/WEST-1/..) -v /home/haziq/GFMPW_2023/WEST-1/dependencies/pdks:/home/haziq/GFMPW_2023/WEST-1/dependencies/pdks -v /home/haziq/GFMPW_2023/WEST-1/caravel:/home/haziq/GFMPW_2023/WEST-1/caravel -v /home/haziq/GFMPW_2023/WEST-1/dependencies/openlane_src:/openlane -v /home/haziq/GFMPW_2023/WEST-1/mgmt_core_wrapper:/home/haziq/GFMPW_2023/WEST-1/mgmt_core_wrapper -e PDK_ROOT=/home/haziq/GFMPW_2023/WEST-1/dependencies/pdks -e PDK=gf180mcuD -e MISMATCHES_OK=1 -e CARAVEL_ROOT=/home/haziq/GFMPW_2023/WEST-1/caravel -e OPENLANE_RUN_TAG=23_12_03_20_59 -e MCW_ROOT=/home/haziq/GFMPW_2023/WEST-1/mgmt_core_wrapper \
efabless/openlane:2023.10.16 sh -c "flow.tcl -design $(realpath ./user_project_wrapper) -save_path $(realpath ..) -save -tag 23_12_03_20_59 -overwrite -ignore_mismatches"
OpenLane 7ea7a2aeef4bea5445d133c26ca2b3e9f0d0c78f
All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.
Available under the Apache License, version 2.0. See the LICENSE file for more details.
[WARNING]: OpenLane may not function properly: open_pdks e0f692f46654d6c7c99fc70a0c94a080dab53571
The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: e0f692f46654d6c7c99fc70a0c94a080dab53571, tested: dd7771c384ed36b91a25e9f8b314355fc26561be)
This may introduce some issues. You may want to re-install the PDK by invoking
make pdkHaziq Rohail
12/04/2023, 2:02 AMI tried removing those layers in lef, without changing gds. But it still fails.
m
Mitch Bailey
12/04/2023, 2:18 AMJust changing the lef should be enough. I think it’s trying to place standard cells but standard cells have been disabled.
Mitch Bailey
12/04/2023, 2:20 AMI think you had output buffering enabled, right? That might not work with
SYNTH_ELABORATE_ONLYMitch Bailey
12/04/2023, 2:23 AMSorry, but could you share your current
openlane/user_project_wrapper/config.jsonh
Haziq Rohail
12/04/2023, 2:24 AMsure.
Haziq Rohail
12/04/2023, 2:28 AMcould it be that my VDD and VSS pins are misplaced/off the PDN grid?
m
Mitch Bailey
12/04/2023, 3:37 AMCan you share
verilog/rtl/user_project_wrapper.vverilog/gl/RO_basic.vh
Haziq Rohail
12/04/2023, 4:49 AMm
Mitch Bailey
12/04/2023, 4:58 AMDoes verilog or yosys complain about the extra comma after
.VSS(vss),user_project_wrapper.v Copy code
RO_basic mprj(
`ifdef USE_POWER_PINS
.VDD(vdd), // User area 1 1.8V power
.VSS(vss), // User area 1 digital ground
`endif
);h
Haziq Rohail
12/04/2023, 5:07 AMnope. The only warnings it gives are:
1. the different pdk version as compared to the one used to test openlane
2. the fact that diode insertion strategy is deprecated.
3. and then the routing error.
Haziq Rohail
12/04/2023, 5:07 AMAnd I just removed that comma.
m
Mitch Bailey
12/04/2023, 12:43 PMIf there’s nothing helpful in
logs/routing/13-detailed.log66 Views