hello, i'm running into a

module $_DLATCH_N_ not found

error when trying to harden my macro i found a message from Tim Edwards in this thread (https://open-source-silicon.slack.com/archives/C03R1GRP9LG/p1668003743813059?thread_ts=1667961859.162959&cid=C03R1GRP9LG) that suggests creating a yosys_mapping.v file and to set SYNTH_EXTRA_MAPPING_FILE to yosys_mapping.v, and i've done that in the macro's config.json file but it does not seem to have made a difference is it just as simple as renaming the module defined in yosys_mapping.v? error:

[STEP 3]
[INFO]: Running Initial Floorplanning (log: ../home/kris/repos/diy-ic/lincoln-gfmpw/openlane/openlane-manchester-baby/runs/23_12_02_20_26/logs/floorplan/3-initial_fp.log)...
[ERROR]: Floorplanning failed
[ERROR]: module $_DLATCH_N_ not found in /home/kris/repos/diy-ic/lincoln-gfmpw/openlane/openlane-manchester-baby/runs/23_12_02_20_26/tmp/merged.nom.lef
[ERROR]: Check whether EXTRA_LEFS is set appropriately

3-inital_fp.log, lines 25-56 basically have the same error:

[WARNING ORD-2013] instance manchester_baby_instance.ram_data_i_0_reg LEF master $_DLATCH_N_ not found.
[WARNING ORD-2013] instance manchester_baby_instance.ram_data_i_10_reg LEF master $_DLATCH_N_ not found.
[WARNING ORD-2013] instance manchester_baby_instance.ram_data_i_11_reg LEF master $_DLATCH_N_ not found.
[WARNING ORD-2013] instance manchester_baby_instance.ram_data_i_12_reg LEF master $_DLATCH_N_ not found.
[WARNING ORD-2013] instance manchester_baby_instance.ram_data_i_13_reg LEF master $_DLATCH_N_ not found.
[WARNING ORD-2013] instance manchester_baby_instance.ram_data_i_14_reg LEF master $_DLATCH_N_ not found.
[WARNING ORD-2013] instance manchester_baby_instance.ram_data_i_15_reg LEF master $_DLATCH_N_ not found.
continued...

yosys_mapping.v:

module \$_DLATCH_P_ (input E, input D, output Q);
  gf180mcu_fd_sc_mcu7t5v0__latq_1 _TECHMAP_DLATCH_P (
    //# {{data|Data Signals}}
    .D(D),
    .Q(Q),

    //# {{clocks|Clocking}}
    .GATE(E)
  );
endmodule

config.json:

{
    "PDK": "gf180mcuD",
	"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
    "DESIGN_NAME": "openlane_manchester_baby",
    "SYNTH_EXTRA_MAPPING_FILE": "dir::src/yosys_mapping.v",
    "VERILOG_FILES": [..list of files..]
    "CLOCK_PORT": "clock",
    "CLOCK_PERIOD": 10.0,
    "DESIGN_IS_CORE": 0,
    "QUIT_ON_UNMAPPED_CELLS": false,
    "DIE_AREA": "0 0 160 160",
    "FP_SIZING": "absolute",

    "GLB_RESIZER_DESIGN_OPTIMIZATIONS": false,
    "GLB_RESIZER_TIMING_OPTIMIZATIONS": false
}

folder structure:

openlane/
├── Makefile
├── openlane-manchester-baby
│   ├── config.json
│   ├── logisim
│   │   ├── circuit
│   │   ├── hdl
│   │   └── hdl_port_io
│   ├── runs
│   │   ├── 23_12_02_19_41
│   │   ├── 23_12_02_19_42
│   │   ├── 23_12_02_20_00
│   │   ├── 23_12_02_20_01
│   │   ├── 23_12_02_20_02
│   │   └── 23_12_02_20_26
│   ├── src
│   │   ├── openlane_manchester_baby.v
│   │   ├── ram_plexer.v
│   │   └── yosys_mapping.v

please let me know if i've missed something, need more info, or if there is a fix that i've managed to miss. thank you :)