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Hi, I need some help in resolving the LVS fails th...
# gf180mcu
n
Hi, I need some help in resolving the LVS fails that I am seeing while hardening the user_project_wrapper, getting the following error
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Contents of circuit 1:  Circuit: 'user_project_wrapper'
Circuit user_project_wrapper contains 112 device instances.
  Class: alpha_soc             instances:   1
  Class: gf180mcu_fd_sc_mcu7t5v0__antenna instances: 111
Circuit contains 623 nets, and 129 disconnected pins.
Contents of circuit 2:  Circuit: 'user_project_wrapper'
Circuit user_project_wrapper contains 112 device instances.
  Class: alpha_soc             instances:   1
  Class: gf180mcu_fd_sc_mcu7t5v0__antenna instances: 111
Circuit contains 289 nets, and 129 disconnected pins.

Circuit 1 contains 112 devices, Circuit 2 contains 112 devices.
Circuit 1 contains 623 nets,    Circuit 2 contains 289 nets. *** MISMATCH ***
These are some of the nets which are not matched
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Net: ANTENNA_mprj_io_in[15]/VNW            |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__antenna/VNW = 1 |                                           
                                           |                                           
Net: ANTENNA_mprj_wbs_cyc_i/VNW            |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__antenna/VNW = 1 |                                           
                                           |                                           
Net: ANTENNA_mprj_io_in[32]/VNW            |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__antenna/VNW = 1 |                                           
                                           |                                           
Net: ANTENNA_mprj_wbs_adr_i[18]/VNW        |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__antenna/VNW = 1 |                                           
                                           |                                           
Net: ANTENNA_mprj_io_in[3]/VNW             |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__antenna/VNW = 1 |
Thanks in advance.
m
Looks like you’ve enabled antenna diode insertion at the top level without enabling fill or decap insertion which also requires power rail connections. The default 
user_project_wrapper
is setup as a wiring only layout which only works if the wires have no antenna rule violations or timing problems. Otherwise, it’s probably better to synthesize the top level.
n
Thanks @Mitch Bailey, that looked to be what was happening but it is strange as I had set
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"GRT_REPAIR_ANTENNAS": 0,
"DIODE_ON_PORTS": "None",
"RUN_HEURISTIC_DIODE_INSERTION": 0,
I had removed the 
DIODE_INSERTION_STRATEGY
after seeing the
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[WARNING]: DIODE_INSERTION_STRATEGY is now deprecated; use GRT_REPAIR_ANTENNAS, DIODE_ON_PORTS and RUN_HEURISTIC_DIODE_INSERTION instead.
thinking that it is not effective. But now after adding it back in and setting it 0, the flow is completed.
👍 1
I am now seeing an LVS issue in precheck though, can you please help in understanding it
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Circuit was modified by parallel/series device merging.
New circuit summary:

Contents of circuit 1:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__aoi221_2'
Circuit gf180mcu_fd_sc_mcu7t5v0__aoi221_2 contains 14 device instances.
  Class: pfet_06v0             instances:   5
  Class: nfet_06v0             instances:   9
Circuit contains 14 nets.
Contents of circuit 2:  Circuit: 'gf180mcu_fd_sc_mcu7t5v0__aoi221_2'
Circuit gf180mcu_fd_sc_mcu7t5v0__aoi221_2 contains 14 device instances.
  Class: pfet_06v0             instances:   5
  Class: nfet_06v0             instances:   9
Circuit contains 14 nets.

Circuit 1 contains 14 devices, Circuit 2 contains 14 devices.
Circuit 1 contains 14 nets,    Circuit 2 contains 14 nets.
It is passing on the platform, its the local that is failing, I guess I will have to wait for the precheck docker to be updated.
m
I don`t see any errors in you previous post.
n
In any case here is the log
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2023-12-01 18:04:46 - [INFO] - LVS output directory: /home/navaneeth/Projects/openmpw/riscv_soc/precheck_results/01_DEC_2023___17_04_18
2023-12-01 18:25:54 - [ERROR] - ERROR LVS FAILED, stat=1, see /home/navaneeth/Projects/openmpw/riscv_soc/precheck_results/01_DEC_2023___17_04_18/logs/LVS_check.log
2023-12-01 18:25:54 - [WARNING] - {{LVS CHECK FAILED}} The design, user_project_wrapper, has LVS violations.
2023-12-01 18:25:54 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/home/navaneeth/Projects/openmpw/riscv_soc/precheck_results/01_DEC_2023___17_04_18/logs'
2023-12-01 18:25:54 - [CRITICAL] - {{FAILURE}} 1 Check(s) Failed: ['LVS'] !!!
LVS_check.log
m
LVS is completing without errors, but 2 cells are missing. By default, netgen matches missing netlists as black boxes.
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Final result: 
Circuits match uniquely.
.
Logging to file "/home/navaneeth/Projects/openmpw/riscv_soc/precheck_results/01_DEC_2023___17_04_18/tmp/lvs.report" disabled
LVS Done.
Warning: device level LVS may be incomplete due to 2 unflattened cell(s): see /home/navaneeth/Projects/openmpw/riscv_soc/precheck_results/01_DEC_2023___17_04_18/outputs/reports/lvs.unflattened
You can look at 
precheck_results/01_DEC_2023___17_04_18/outputs/reports/lvs.unflattened
to see which cells are missing and add the spice or verilog to 
lvs/user_project_wrapper/lvs_config.json
. With verilog, be sure to list lower level cells before parent files.
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