i tried fixing this error ,but any changes that i made in config json didnot fix it,kindly help. here is my config.json, { "DESIGN_NAME": "mk_ram_instances", "VERILOG_FILES": "dir::src/*.v", "CLOCK_PORT": "CLK", "CLOCK_PERIOD": 13.0, "FP_SIZING": "absolute", "DIE_AREA": "0 0 4500 4525", "FP_PDN_VPITCH": 25, "FP_PDN_HPITCH": 25, "FP_PDN_VOFFSET": 5, "FP_PDN_HOFFSET": 5, "DESIGN_IS_CORE": false, "FP_PDN_CORE_RING": false, "SYNTH_AUTONAME" : 1 } its been an unfixed issue from 3 days from myside

Are you trying to automatically place macros? You haven’t specified any hard macros, so everything will be flattened and synthesized. Is that what you want?

sir actaually this is the macro to the top module , to break it dowm ,there are no other submodules used , so i want it in one shot of run. and when i tried synth_no_flat,still i got error

Are you able to share your verilog in

src/*.v

?

may be i cant share sir! its not my design,its a company's design. felt sorry