Hi people, i am new to this klayout design thing and i am trying to implement a common centroid design on GF180 for a voltage divider (2:1) but i am not sure if this implementation idea would correctly override the gradients. Does anyone have any suggestions or good references to analyze this and its wiring? thanks in advance

The voltage divider that Max is showing has a ratio of 4:7. When we designed it, we thought about the regularity of the pattern and the concept of the common centroid. We don't know if there are more rules associated with this layout technique. @Boris Murmann @Mitch Bailey @Amro Tork

Sorry, outside of my expertise.

We are exploring with 3:5 also, do you think this it's ok?

How large is this structure? This matters a lot for the significance of gradients. All this stuff on gradients was written 40 years ago and everyone keeps copying it without looking at real data.

Our ppoly_r grid should be something like this, 10x1 um each cell. Another posibility would be just using 2 rows instead of 4, and each cell would be 20x1. Which book or reference do you recommend for this task? Thanks for the quick response

@aquiles viza https://www.amazon.com/Art-Analog-Layout-Alan-Hastings/dp/0130870617

Swap the first and second rows. You should have symmetry in the y-axis also. Something very important you should look at is the possibility of calibration. This voltage divider ratio could be variable, if you implement switches.

@Luis Henrique Rodovalho Swaping the first and second row gives something like this, thanks for the advice

@aquiles viza, now that I see it, I've realized that the previous configuration is actually better.

One way to check a common-centroid structure is to find the average x-y center point of all the "A" transistors and make sure it is the same x-y center point of all the "B" transistors. You will also want to put "dummy" transistors, that are electrically wired off, completely around your structure so that the outside edges of you "A-B" layout looks exactly the same as the edges of the transistors in the middle of you "A-B" array. One last detail to to make sure the direction of current flow is also common-centroided.