Nam Nguyễn Hồ Giang
11/28/2023, 5:12 AMNam Nguyễn Hồ Giang
11/28/2023, 5:13 AMVijayan Krishnan
11/28/2023, 5:20 AMissue_reproducible
generated inside the run directory to debug the issueMitch Bailey
11/28/2023, 5:20 AM"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
and
"FP_PDN_MACRO_HOOKS": "<instance> vccd1 vssd1 <macro_power> <macro_ground>",
to your config.json
file.Mitch Bailey
11/28/2023, 5:43 AMfeedback save <file_name>
<file_name>
.Nam Nguyễn Hồ Giang
11/28/2023, 5:57 AMVijayan Krishnan
11/28/2023, 6:01 AMissue_reproducible
directory and attach here for experts to debug. Also consider Mitch comments as your design includes macrosNam Nguyễn Hồ Giang
11/28/2023, 6:07 AMNam Nguyễn Hồ Giang
11/28/2023, 6:12 AMMitch Bailey
11/28/2023, 7:19 AMuser_proj_example
verilog rtl to see how to use ``ifdef USE_POWER_PINS`Nam Nguyễn Hồ Giang
11/28/2023, 7:43 AMNam Nguyễn Hồ Giang
11/28/2023, 7:44 AMMitch Bailey
11/28/2023, 8:05 AMmy_project_wrapper
will use all 5 metal layers, but my_project
should only use up to metal4 and macro1
and macro2
should only use up to metal3.
my_project
should use metal4 to connect to the metal3 power rails in macro1
and macro2
.
my_project_wrapper
will use metal5 to connect to the metal4 power rails in my_project
, but won’t connect directly to macro1
and macro2
.Nam Nguyễn Hồ Giang
11/28/2023, 9:52 AMMitch Bailey
11/28/2023, 9:58 AMruns/<tag>/logs/signoff/42-lvs.lef.log
?Nam Nguyễn Hồ Giang
11/28/2023, 10:26 AMMitch Bailey
11/28/2023, 10:43 AMNumber of nets: 25017 **Mismatch** |Number of nets: 25015 **Mismatch**
Probably these
Net: sm/vccd1
synapse_matrix_design/vccd1 = 1
Net: sm/vssd1
synapse_matrix_design/vssd1 = 1
Can you verify that the sm
macro is not connected to power (in the layout)?Nam Nguyễn Hồ Giang
11/29/2023, 4:32 AMMitch Bailey
11/29/2023, 4:38 AMconfig.json
file or a repo link?Nam Nguyễn Hồ Giang
11/29/2023, 4:48 AMNam Nguyễn Hồ Giang
11/29/2023, 4:50 AMMitch Bailey
11/29/2023, 5:01 AM