Hello. I tried to put macros into my project. I ha...
# openlane
n
Hello. I tried to put macros into my project. I have finished placing the macros and setting up the config.json. I proceed to run openlane for synthesis and tapeout. I get a Running Global Routing error code. Specifically, the error: [ERROR GRT-0119] Routing congestion too high. Check the congestion heatmap in the GUI and load /home/edabk/efabless/caravel_user_project/openlane/neuron_core_dffram/runs/23_11_28_11_46/tmp/routing/groute-congestion.rpt in the DRC viewer.
@Mitch Bailey please help me!
v
attach
issue_reproducible
generated inside the run directory to debug the issue
❤️ 1
m
I’m guessing that the macro is too close to the edge. Does anything change if you center it? Also, you’ll probably want to add
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"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
and
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"FP_PDN_MACRO_HOOKS": "<instance> vccd1 vssd1 <macro_power> <macro_ground>",
to your
config.json
file.
❤️ 1
If you’re extracting manually, use
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feedback save <file_name>
to save the results in
<file_name>
.
(wrong thread)
n
@Vijayan Krishnan I saw thI saw that folder. but I don't know how to debugat folder. but I don't know how to debug
v
zip the
issue_reproducible
directory and attach here for experts to debug. Also consider Mitch comments as your design includes macros
❤️ 1
n
@Mitch Bailey Is it necessary to add power pins in my design? I proceed to incorporate the macro into my design and then create a new macro to incorporate into user_project_wrapper
issue_reproducible.zip
m
Right. Refer to the sample
user_proj_example
verilog rtl to see how to use ``ifdef USE_POWER_PINS`
n
Thanks for helping. I was able to run full flow
👍 1
@Mitch Bailey but, i have a question. my project is in the form of a diagram. I know that my project must have pin power set up. But does my macro really need battery power? If so, why do we need to configure the power pin for macros?
m
There may be ways to route the power other than the following explanation. For each level of routing, you loose a routing layer.
my_project_wrapper
will use all 5 metal layers, but
my_project
should only use up to metal4 and
macro1
and
macro2
should only use up to metal3.
my_project
should use metal4 to connect to the metal3 power rails in
macro1
and
macro2
.
my_project_wrapper
will use metal5 to connect to the metal4 power rails in
my_project
, but won’t connect directly to
macro1
and
macro2
.
n
@Mitch Bailey. Thank you for your support. I followed the steps you showed, but unfortunately, I'm getting an error in step runnin LVS. Let me ask if yes, what causes this error and how to fix it
m
Can you share
runs/<tag>/logs/signoff/42-lvs.lef.log
?
n
42-neuron_core_dffram.lef.lvs.log
m
There are 2 more nets in the layout than in the source verilog
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Number of nets: 25017 **Mismatch**         |Number of nets: 25015 **Mismatch**
Probably these
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Net: sm/vccd1                           
  synapse_matrix_design/vccd1 = 1         
                                                                 
Net: sm/vssd1                                     
  synapse_matrix_design/vssd1 = 1
Can you verify that the
sm
macro is not connected to power (in the layout)?
n
@Mitch Bailey Exactly. Thank you, I saw. And I have some questions. Inside the "sm" macro, I used the "ram0" macro synthesized from the DFFRAM framework. I noticed that DFFRAM doesn't have a power pin after I synthesized it. When I leave power to "ram0" does the macro not have a big impact on the circuit? If it greatly affects the circuit, please show me how to assign power pins to "ram0" macro during synthesis using DFFRAM framework
m
Not familiar with the DFFRAM framework. Do you have a
config.json
file or a repo link?
n
i use the repo to create macro "ram0"
m
Probably best to ask the repo maintainers how to handle power generation. I think the sky130 caravel uses a DFFRAM. you might take a look at that.