Hi I am trying to run post layout simulation using the powered verilog generated by openlane. I have included the gf180mcuD cells definition but I am getting error on the power and ground connections of the cells. The issue I think is that the simulator is picking up the functional definition of cells without the power connections defined rather than the one with power connections defined. Is there a way to force the simulator to pick up the correct definitions. @Mitch Bailey @Tim Edwards

There should be a powered and unpowered version of the post-synthesis(=layout) verilog. I’m not sure what merit there is to running simulation on a powered verilog netlist. What library are you including for the standard cells?

$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v

has

ifdef

blocks for

FUNCTIONAL

and

USE_POWER_PINS

. Are either of these set in your simulation environment?

My apologies for the late reply but the parameter USE_POWER_PINS was not set hence the error, thanks for the help and apologies again