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GPIO-Defines check is failing while runnig the pre...
# shuttle-precheck
n
Hi, I am new to efabless tape out process and the use of open source tools. I have designed a two stage opamp to understand the design and tape out process for analog circuits. While running precheck locally, the GPIO-Defines check is failing. I have edited the user_defines.v file as suggested but the error is still present. Please see the attached user_define.v file and precheck log. Moreover, the precheck is not running LVS. The caravel was initially installed for digital designs (MPW8) with user_project_wrapper but I cloned an user_analog_project_wrapper and followed the steps with the old CARAVEL_ROOT path. Is that creating the issue? Please help me with the issue.
user_defines.v
Please see the precheck log here.
precheck.log
m
The verilog constants defined with ``define` must be preceded with
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.
Try changing
````define USER_CONFIG_GPIO_15_INIT GPIO_MODE_USER_STD_ANALOG
to
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`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_USER_STD_ANALOG
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n
It worked. Thanks a lot Mitch Bailey The precheck is passed locally. But it is still not running LVS. Any idea why?
m
Is 
DISABLE_LVS
set? 
echo $DISABLE_LVS
n
There is no variable defined named DISABLE_LVS
I did not find anything for LVS in mpw_precheck.py. Do I need any updated file?
Hey Mitch Bailey I found out why the lvs is not running during precheck. The checks folder inside mpw_precheck does not have any folder for lvs and oeb. That is why they are not running. I will clone them and run precheck.
m
If you’re using an up-to-date 
Makefile
, 
make precheck
will pull the latest version.
n
Hi Mitch Bailey. Sorry for the late reply. Thank you for the answer. How to check whether the Makefile is recent or not?
m
For gfmpw-1,
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curl <https://raw.githubusercontent.com/efabless/caravel_user_project/gf180mcu/Makefile> > Makefile
n
Mitch Bailey I have updated the mpw_precheck and the OEB and LVS checks are running now. I am working on fixes since both are failing. Thank you so much for all the help.
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m
Please let me know if anything is unclear.
n
Mitch Bailey, The LVS and OEB checks are failing. But there is no log created for them to see the error. During precheck this error is coming : <class 'json.decoder.JSONDecodeError'>. I have attached the precheck log. Can you please help me with the error?
precheck.log
Here is the used lvs_config.json file.
lvs_config.json
m
json files are really strict on syntax. You shouldn’t need 
LVS_SPICE_FILES_TO_FIX
so try changing
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"LVS_SPICE_FILES_TO_FIX": [
		
	],
	"LVS_SPICE_FILES": ["/home/zerotoasic/naina/user_analog_project_wrapper/lvs/opamp.spice",
	"/home/zerotoasic/naina/user_analog_project_wrapper/lvs/user_analog_project_wrapper.spice"
	],
		""
to
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"LVS_SPICE_FILES": ["/home/zerotoasic/naina/user_analog_project_wrapper/lvs/opamp.spice",
	"/home/zerotoasic/naina/user_analog_project_wrapper/lvs/user_analog_project_wrapper.spice"
	],
n
Mitch Bailey, I have changed the .json file as suggested but there is no change in the problem. The changed .json file is attached. I could not find any config file as : "INCLUDE_CONFIGS": [ "$LVS_ROOT/tech/$PDK/lvs_config.base.json". Is that the problem?
lvs_config.json
But the decode error is gone. I think I have to define $UPRJ_ROOT now.
precheck.log
That was the issue. OEB_check.log is getting generated now :)
👍 1
m
So the LVS and OEB checks are passing?
n
No, the checks are not passing. Just the logs are generating now.
Mitch Bailey, I am not using any GPIO pins. The opamp is using only power pins and user analog pins for connections. In this case, what should I do with oeb pins. Is any connection required even though I am not using any GPIO pins?
m
If you’re only using analog connections, the OEB check should only be showing warnings.
Some of the 
io_out
and 
io_oeb
connections have been buffered. If you don’t connect them, there’s a possibility of leakage through the buffer nmos and pmos. If you’re not concerned about power consumption, you might be able to ignore that.
n
Ok. I will leave them as it is for now since I have other fixes to do. Can you please have look at the logs?
OEB_check.log
Here is the other one.
LVS_check.log
Mitch Bailey, there is one issue common in all errors is "Call to undefined subcircuit sky130_fd_pr__pfet_g5v0d10v5". Which spice file needs to included for the cell g5v0d10v5. I have included "$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice" in .json file. Is it the correct one?
m
1. Does your top layout 
user_analog_project_wrapper
have all the necessary ports? If you’re missing the top ports, LVS won’t extract a top subckt and CVC/OEB won’t run. If you have 
user_analog_project_wrapper_empty
, that has all the text and pins and you can flatten that. 2. In your lvs_config file, It looks like you have both spice files (extracted from layout?) and verilog files. You probably don’t want both and rarely if ever should use extracted layouts as source for LVS. Do you have schematics created from xschem? These are what you should use for LVS.
n
Ok. Thank you MItch Bailey. Then, is there no need to write a verilog code file if extracted spice file is used. Where to define the schematic from xschem? In lvs_config.json file?
I have used user_analog_project_wrapper_empty only.
Please see the extracted spice netlist from gds. It does contain all the top ports.
user_analog_project_wrapper.spice
Mitch Bailey, I got the issue, the config file was not giving the correct path for the spice file. Now the LVS is failing top level pin matching even though same pins are present in gds and spice files. Please have a look at LVS report.
lvs.report
m
For LVS, the extracted spice file is located at 
precheck_results/<tag>/tmp/ext/user_analog_project_wrapper.gds.spice
Then, is there no need to write a verilog code file if extracted spice file is used.
The purpose of LVS is to check the layout versus the design data. The extracted spice file you shared above should not be used for LVS. Do you have an xschem schematic for 
user_analog_project_wrapper
?
n
Yes I have an xschem schematic and xschem spice file as well. When I ran LVS locally, using xschem spice file and extracted spice netlist from gds it was matching. LVS was clear while running locally. Why user_analog_project_wrapper.gds.spice does not have any top level pins. When I run ext2spice locally, all the pins are extracted correctly.
Here is the generated spice file.
user_analog_project_wrapper.gds.spice
Mitch Bailey, In precheck_results/<tag>/tmp/ext/user_analog_project_wrapper.ext all the pins are extracted as nodes.
m
Just to be clear,
When I ran LVS locally, using xschem spice file and extracted spice netlist from gds
You had a gds file (not a mag file) that you loaded into magic and extracted that with a 
ext2spice
manually without using an LVS script?
n
Mitch Bailey, I read the gds in magic and then extracted spice file using ext2spice. It is reading all the top ports correctly. Please see the file attached.
user_analog_project_wrapper.spice
But the spice file extracted during the precheck looks like this.
user_analog_project_wrapper.gds.spice
Thank you so much for help :)
m
What version of the pdk are you using? (If you’ve installed with volare, 
volare ls
, if not 
cat $PDK_ROOT/$PDK/SOURCES
).
n
volare ls /home/zerotoasic/asic_tools/pdk/volare/sky130/versions └── 3af133706e554a740cfe60f21e773d9eaa41838c (UNKNOWN) (enabled)
Mitch Bailey, Please see the xschem schematic.
Is using older version of pdk affecting spice file generation during precheck?
Mitch Bailey, there is a remove_disconnect.awk file in /mpw_precheck/checks/be_checks/scripts folder. WHat does it do?
m
That is a possibility.
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3af133706e554a740cfe60f21e773d9eaa41838c (2022.11.08)
Looks like that pdk was from last year. What tool did you use to create the gds?
n
Magic 8.3.331
m
The 
remove_disconnect.awk
script is used in the soft connection check. The layout is extracted twice, once normally and once with a special rule set that ignores well connections. The well connections from the normally extracted netlist are removed and the netlists are compared. Any mismatches are caused by high resistance well connections. When the well connections are removed, some nets become disconnected. The script removes these disconnected nets. If you are planning to submit to a shuttle, please be sure that the 
Makefile
(and thus the PDK) are the correct version.
n
Thank you Mitch Bailey. Can you please tell me how to update the pdk? Will updating pdk, update all the schematics and layouts to the latest version as well?
Mitch Bailey, There is one think I noticed. When I use extract all on complete gds with analog wrapper, it says this: extract all Extracting sky130_fd_pr__pfet_g5v0d10v5_766NZ5 into /home/zerotoasic/naina/Magic_scrh/sky130_fd_pr__pfet_g5v0d10v5_766NZ5.ext: Extracting sky130_fd_pr__nfet_g5v0d10v5_DTEAGN into /home/zerotoasic/naina/Magic_scrh/sky130_fd_pr__nfet_g5v0d10v5_DTEAGN.ext: Extracting sky130_fd_pr__pfet_g5v0d10v5_2S4URJ into /home/zerotoasic/naina/Magic_scrh/sky130_fd_pr__pfet_g5v0d10v5_2S4URJ.ext: Extracting sky130_fd_pr__nfet_g5v0d10v5_84HAUK into /home/zerotoasic/naina/Magic_scrh/sky130_fd_pr__nfet_g5v0d10v5_84HAUK.ext: Extracting sky130_fd_pr__nfet_g5v0d10v5_86HAUK into /home/zerotoasic/naina/Magic_scrh/sky130_fd_pr__nfet_g5v0d10v5_86HAUK.ext: Extracting opamp into /home/zerotoasic/naina/Magic_scrh/opamp.ext: Extracting user_analog_project_wrapper into user_analog_project_wrapper.ext: user_analog_project_wrapper: 36 warnings Total of 36 warnings.
Can these warnings be causing the issue?
m
Make sure you haven’t overridden any of the environment variables and download the latest 
Makefile
.
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curl <https://raw.githubusercontent.com/efabless/caravel_user_project/main/Makefile> > Makefile
env | grep TAG
env | grep COMMIT
env | grep ROOT
and then rerun
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make setup
Looks like the post doesn’t have the warning messages you mentioned.
n
Hi Mitch Bailey. I updated the pdk using volare. I also updated magic to the latest version. Now the precheck is passed while runnig locally including LVS and OEB checks.
Thank you so much for help. :)
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Regarding the warning message ... no warning are listed in magic while extraction. It just says "Total of 36 warnings"
m
For precheck, the warnings should be in 
precheck_results/<tag>/ext/<top_cell>-ext2gds.spice.feedback.txt
Warnings like this are generated for mos capacitors that only have one source/drain.
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feedback add "device missing 1 terminal;
If you’re extracting manually, use
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feedback save <file_name>
to save the results in 
<file_name>
.
n
Ok.
Thank you.
Hey Mitch Bailey, I have one question. For my analog design, I have not used openlane route. I just did everything manually. I did not see anything regrading antenna check during precheck. Can you please tell me how the antenna check is done for analog design if the openlane is not used?
m
Good question. @Marwan Abbas does precheck do any antenna drc checks?
n
Mitch Bailey, My design did have antenna errors but it was not reported during precheck. Precheck was clean on efabless.
Later I used antennacheck in magic and fixed errors.
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m
Thanks for reporting this!
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