@Barak Hoffer @Stefan Schippers There is a serious issue with the reram ngspice model. If I put vdd with 0 volt below BE pin as a probe, the simulation aborted with convergence failing, and a ridiculous current was plotted on the probe. I guess the terms I(nfilament, BE) and I(nT, BE) cause the problem. Do such currents necessarily get through the BE pin? I think this approach could cause vulnerability.

seems like a bug for the model. Normally, a reram device won’t behave that way.

I suggest trying a well-posed model such as https://github.com/akashlevy/WP-RRAM-SPICE-Model which was developed by folks at berkeley a while back. the model in my repo should be calibrated to skywater rram

It is already supposed to be well-posed. I think the problem is convergence in some cases, I am trying to improve it. You can try and play with the step size and initial condition to get a working simulation.

Are you using the Verilog-A (OSDI) ReRAM model with a version of ngspice supporting OSDI model loading?

@Tim Edwards I think so. I use ngspice version 41

I have added a 0V ammeter as you did (tried both ammeter orientations) but transient analysis was not affected at all, same results, same simulation time.

@Stefan Schippers could you attach the verilog-a file that you are using? I want to run it in my environment.

Sure, here the whole git workspace i am using. I have not updated to latest, so this is the exact one I am using here.

@Stefan Schippers @Barak Hoffer I got the same result as yours using the model you attached. However, the current that flows through the 'v2#branch' still shows ridiculous forms. Also, simply switching the position of R1 and reram_cell yields convergence failure. Did you check 'plot i(v2)' which is directly attached to BE? Please check.

I have checked the current through the voltage source, but it is consistent. see attached image.