Hi, I just did a new project setup and tried running the user_project_example however its failing at STEP 9. During the build I see that the openroad process starts consuming all the system memory and my laptop becomes unresponsive, so I think the OS kills the process but I guess this should not be happening.

navaneeth@raptor:riscv_soc$ make user_proj_example
make -C openlane user_proj_example
make[1]: Entering directory '/home/navaneeth/.local/share/Trash/files/riscv_soc/openlane'
# user_proj_example
mkdir -p ./user_proj_example/runs/23_11_18_00_15 
rm -rf ./user_proj_example/runs/user_proj_example
ln -s $(realpath ./user_proj_example/runs/23_11_18_00_15) ./user_proj_example/runs/user_proj_example
docker run -it -u $(id -u $USER):$(id -g $USER) -v $(realpath /home/navaneeth/.local/share/Trash/files/riscv_soc/..):$(realpath /home/navaneeth/.local/share/Trash/files/riscv_soc/..) -v /home/navaneeth/asic/pdk:/home/navaneeth/asic/pdk -v /home/navaneeth/.local/share/Trash/files/riscv_soc/caravel:/home/navaneeth/.local/share/Trash/files/riscv_soc/caravel -v /home/navaneeth/asic/openlane:/openlane -v /home/navaneeth/.local/share/Trash/files/riscv_soc/mgmt_core_wrapper:/home/navaneeth/.local/share/Trash/files/riscv_soc/mgmt_core_wrapper -e PDK_ROOT=/home/navaneeth/asic/pdk -e PDK=gf180mcuC -e MISMATCHES_OK=1 -e CARAVEL_ROOT=/home/navaneeth/.local/share/Trash/files/riscv_soc/caravel -e OPENLANE_RUN_TAG=23_11_18_00_15 -e MCW_ROOT=/home/navaneeth/.local/share/Trash/files/riscv_soc/mgmt_core_wrapper  \
	efabless/openlane:2023.07.19-1 sh -c "flow.tcl -design $(realpath ./user_proj_example) -save_path $(realpath ..) -save -tag 23_11_18_00_15 -overwrite -ignore_mismatches"
OpenLane 30ee1388932eb55a89ad84ee43997bfe3a386421
(with mounted scripts from d054702b2cce04761cc2bc598f6b95c9d8ca7c6c)
All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.
Available under the Apache License, version 2.0. See the LICENSE file for more details.

[INFO]: Using configuration in '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/config.json'...
[INFO]: PDK Root: /home/navaneeth/asic/pdk
[INFO]: Process Design Kit: gf180mcuC
[INFO]: Standard Cell Library: gf180mcu_fd_sc_mcu7t5v0
[INFO]: Optimization Standard Cell Library: gf180mcu_fd_sc_mcu7t5v0
[WARNING]: SYNTH_MAX_FANOUT is now deprecated; use MAX_FANOUT_CONSTRAINT instead.
[WARNING]: DIODE_INSERTION_STRATEGY is now deprecated; use GRT_REPAIR_ANTENNAS, DIODE_ON_PORTS and RUN_HEURISTIC_DIODE_INSERTION instead.
[INFO]: DIODE_INSERTION_STRATEGY set to 4. Setting RUN_HEURISTIC_DIODE_INSERTION to 1
[INFO]: DIODE_INSERTION_STRATEGY set to 4. Setting DIODE_ON_PORTS to in
[INFO]: Run Directory: /home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15
[INFO]: Saving runtime environment...
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[WARNING]: PDK 'gf180mcuC', SCL 'gf180mcu_fd_sc_mcu7t5v0' will generate errors with instantiated stdcells in the design.
[WARNING]: Either disable QUIT_ON_LINTER_ERRORS or remove the instantiated cells.
[INFO]: Running linter (Verilator) (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/synthesis/linter.log)...
[INFO]: 0 errors found by linter
[WARNING]: 9 warnings found by linter
[STEP 1]
[INFO]: Running Synthesis (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/synthesis/1-synthesis.log)...
[STEP 2]
[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/synthesis/2-sta.log)...
[STEP 3]
[INFO]: Running Initial Floorplanning (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/floorplan/3-initial_fp.log)...
[INFO]: Floorplanned with width 2786.56 and height 1724.8.
[STEP 4]
[INFO]: Running IO Placement (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/floorplan/4-place_io.log)...
[STEP 5]
[INFO]: Running Tap/Decap Insertion (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/floorplan/5-tap.log)...
[INFO]: Power planning with power {vccd1} and ground {vssd1}...
[STEP 6]
[INFO]: Generating PDN (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/floorplan/6-pdn.log)...
[STEP 7]
[INFO]: Running Global Placement (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/placement/7-global.log)...
[STEP 8]
[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/placement/8-gpl_sta.log)...
[STEP 9]
[INFO]: Running Placement Resizer Design Optimizations (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/placement/9-resizer.log)...
[ERROR]: during executing openroad script /openlane/scripts/openroad/resizer.tcl
[ERROR]: Log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/placement/9-resizer.log
[ERROR]: Last 10 lines:
Using 1e+00 for voltage...
Using 1e-03 for current...
Using 1e-06 for power...
Using 1e-06 for distance...
Reading design constraints file at '/home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/tmp/floorplan/3-initial_fp.sdc'…
[INFO]: Setting RC values...
[INFO RSZ-0027] Inserted 58 input buffers.
[INFO RSZ-0028] Inserted 65 output buffers.
[INFO RSZ-0058] Using max wire length 9189um.
child killed: kill signal

[ERROR]: Creating issue reproducible...
[INFO]: Saving runtime environment...
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Parsing config file(s)…
Setting up /home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/issue_reproducible…
[WRN] /home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/tmp/placement/9-resizer.sdc was not found, might be a product. Skipping
Done.
[INFO]: Reproducible packaged: Please tarball and upload '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/issue_reproducible' if you're going to submit an issue.
[ERROR]: Step 9 (placement) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "run_tcl_script" line 219)
    invoked from within
"run_tcl_script -tool openroad -no_consume {*}$args"
    (procedure "run_openroad_script" line 2)
    invoked from within
"run_openroad_script $::env(SCRIPTS_DIR)/openroad/resizer.tcl -indexed_log [index_file $::env(placement_logs)/resizer.log] -save "to=$::env(placement_t..."
    (procedure "run_resizer_design" line 8)
    invoked from within
"run_resizer_design"
    (procedure "run_placement" line 17)
    invoked from within
"run_placement"
    (procedure "run_placement_step" line 8)
    invoked from within
"run_placement_step"} -errorline 1
[INFO]: Saving current set of views in '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/results/final'...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/reports/manufacturability.rpt'.
[INFO]: Created metrics report at '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.
[INFO]: The failure may have been because of the following warnings:
[WARNING]: PDK 'gf180mcuC', SCL 'gf180mcu_fd_sc_mcu7t5v0' will generate errors with instantiated stdcells in the design.
[WARNING]: Either disable QUIT_ON_LINTER_ERRORS or remove the instantiated cells.
[WARNING]: 9 warnings found by linter

make[1]: *** [Makefile:79: user_proj_example] Error 255
make[1]: Leaving directory '/home/navaneeth/.local/share/Trash/files/riscv_soc/openlane'
make: *** [Makefile:123: user_proj_example] Error 2

Any pointers is appreciated.

File a GitHub issue with issue_reproducible generated in the run directory

To answer my own question, this issue did not appear when I created my project again from the template repository (

caravel_user_project

) but this time with all the branches and then switching the branch to

gf180mcu

after cloning