How can I generate a pad frame around my design in order to perform full chip simulation?

Are you referring to verilog simulation or spice simulation? For verilog simulation, the full chip is in

caravel/verilog/rtl/caravel.v

. You’ll need to make sure it references your

user_project_wrapper

and not the default.

I was referring to SPICE simulation. Suppose, I have a full custom circuit designed using magic which contains some custom built components and some blocks generated through OpenLane. All these are routed together manually. I want to generate a pad frame in which this design can fit. Then, I want to combine the design and pad frame inside magic and route the signals manually. Then, I want to simulate the full chip using ngspice. In the above scenario, I don't know how to generate a pad frame.

So you’re talking about a custom pad frame. There have been public designs that have used their own internal pad frames.

Is it possible to do something like this in OpenLane - http://www.futureware.at/~philipp/vsd2018/VSDOpen%2718_5_Guehring.pdf

You can use user area independent from the caravel frame. You could put your own pads there, but wouldn’t be able to use any packaged devices. You’d have to come up with some way to access the pads on a bare chip - maybe a probe station?

Thank you for the help. I appreciate that.