Hello all, I'm trying to achieve LVS match of the two netlists attached using netgen, without success... my first time doing manual layout with standard cells, so no idea if anythign special should be done - for example it mentions black boxes, no idea if this is as it should be:

Circuit 1 cell sky130_fd_sc_hd__clkdlybuf4s50_2 is a black box; will not flatten Circuit 2

Warning: Equate pins:  cell sky130_fd_sc_hd__clkdlybuf4s50_2 is a placeholder, treated as a black box.

I'm working on the IIC-OSIC tools docker, with the following command: "netgen -batch lvs "/foss/designs/Open3LFCC_V2_GD12V/LS_boot_20230921/sch/sp_delay_sch.spice sp_delay" "/foss/designs/Open3LFCC_V2_GD12V/magic/tcl/sp_delay_lyt.spice sp_delay" /foss/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl lvs_delay.log" I'm attaching below the .log file in case anyone can take a look, any help would be greatly appreciated!

You haven't given netgen a description of the standard cells on the schematic side. There are several ways to do this; you can read it into netgen separately (which is a bit more complicated, because you have to prepare a script for LVS, which is no longer a single command line), or (the easiest way) you can simply add

.include /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice

to your schematic netlist.

Ok, i'll try this, thanks!

@Jorge Marin Maybe you don’t have ports defined in the layout? See this thread.